A good, continuous ground plane would be a very good idea. The ground plane of the output stage board should be directly attached to the ground plane of the dac board. Did you take a look at how I did that for the through-hole output stage design I made at request of some forum members? Also, if you carefully read what ESS has to say about output stage opamps in relation to the dac chip, its about the same as what I did. Many people fail to study the pertinent information: http://www.esstech.com/files/4514/4095/4306/Application_Note_Component_Selection_and_PCB_Layout.pdf
EDIT: By the way, a single-channel 40MHz scope for free is a pretty nice addition to the tool kit. It can be used for many things, so learn everything you can about what it can do, how to configure it for different measurements, and general use of 10x probes. Some good info in: https://download.tek.com/document/02_ABCs-of-Probes-Primer.pdf
Also: http://ecelabs.njit.edu/student_resources/XYZ-Scope.pdf
EDIT: By the way, a single-channel 40MHz scope for free is a pretty nice addition to the tool kit. It can be used for many things, so learn everything you can about what it can do, how to configure it for different measurements, and general use of 10x probes. Some good info in: https://download.tek.com/document/02_ABCs-of-Probes-Primer.pdf
Also: http://ecelabs.njit.edu/student_resources/XYZ-Scope.pdf
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Hi Mark,
I downloaded the ”throw hole” file, for some reason my computer flag it for a virus, so i didn’t read it..
I will take a look at the guides about the scooe you attached.
BR //Daniel
I downloaded the ”throw hole” file, for some reason my computer flag it for a virus, so i didn’t read it..
I will take a look at the guides about the scooe you attached.
BR //Daniel
There is no virus in the through hole download, nothing executable at all. Your antivirus program is reporting a false positive if anything.
Its just a zip file mainly with an .rtf file that can be read with Wordpad or any number of other programs. It contains text and pictures of my output stage project in various stages of completion.
One of the pics showing how the two ground planes are attached can be seen below below.
Its just a zip file mainly with an .rtf file that can be read with Wordpad or any number of other programs. It contains text and pictures of my output stage project in various stages of completion.
One of the pics showing how the two ground planes are attached can be seen below below.
Attachments
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Nice work.
Stupied anti virus..
Do you have the posibility to post the link again to the zip file?
BR // Daniel
Stupied anti virus..
Do you have the posibility to post the link again to the zip file?
BR // Daniel
Hi Daniel it could be great maybe a small group buy with your output Pcb's if you have time to optimize it bit with help from forum members😊
Thx
Happy building
Sure, let me try it then we can see if it’s something to procced with ��
BR // Daniel
BR // Daniel
Hello,
When waiting for my test PCB for i/v stage i was thinking of testning the simple stage in the Link that you Mark linked to long ago.
http://www.esstech.com/files/4514/4095/4306/Application_Note_Component_Selection_and_PCB_Layout.pdf
Figure 3. It uses 12v and GND. Will 15v and GND work also without any modifikation?
BR // Daniel
When waiting for my test PCB for i/v stage i was thinking of testning the simple stage in the Link that you Mark linked to long ago.
http://www.esstech.com/files/4514/4095/4306/Application_Note_Component_Selection_and_PCB_Layout.pdf
Figure 3. It uses 12v and GND. Will 15v and GND work also without any modifikation?
BR // Daniel
Daniel,
IIRC, don't think anyone ever got that circuit to work. I know ESS does not use it on its ES9038PRO evaluation board. Besides, if it did work why wouldn't the cheap Chinese dac boards use it? Its simpler than the awful sounding voltage mode circuit they are using on the board you are planning to mod.
IIRC, don't think anyone ever got that circuit to work. I know ESS does not use it on its ES9038PRO evaluation board. Besides, if it did work why wouldn't the cheap Chinese dac boards use it? Its simpler than the awful sounding voltage mode circuit they are using on the board you are planning to mod.
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Hi,
I solder Victors I/V stage from the 9018 thread. Also did the avcc mod.
We tried the Dac yesterday evening and the sound was really ok.
One problem appiered, we use optical input and after one hour we start to drop ”lock”.
Every 3-6 second a click sound and the lock led flashed for half half a second.
Maybe a bad solder?
BR// Daniel
I solder Victors I/V stage from the 9018 thread. Also did the avcc mod.
We tried the Dac yesterday evening and the sound was really ok.
One problem appiered, we use optical input and after one hour we start to drop ”lock”.
Every 3-6 second a click sound and the lock led flashed for half half a second.
Maybe a bad solder?
BR// Daniel
Hi Daniel,
AVCC and the output stage should have no effect on 'Lock' status of the dac chip. Optical goes into the optical receiver and from there goes through a minimal number of passive components and then directly into one of the pins of the dac chip. Also, the optical receiver is powered by 3.3v from the dac board. I would suggest to look at the signal coming out of the optical receiver with a scope both when 'lock' operation is okay and when a fault is indicated. If you see a change in the signal on the scope, most likely that would indicate a problem with the optical receiver, optical cable, or the source device. Either that or maybe the 3.3v to the optical receiver is intermittent (doesn't seem likely).
AVCC and the output stage should have no effect on 'Lock' status of the dac chip. Optical goes into the optical receiver and from there goes through a minimal number of passive components and then directly into one of the pins of the dac chip. Also, the optical receiver is powered by 3.3v from the dac board. I would suggest to look at the signal coming out of the optical receiver with a scope both when 'lock' operation is okay and when a fault is indicated. If you see a change in the signal on the scope, most likely that would indicate a problem with the optical receiver, optical cable, or the source device. Either that or maybe the 3.3v to the optical receiver is intermittent (doesn't seem likely).
Thanks,
We tested the cable and source with another dac and there were no problem then.
Also it seams like the problem came/was worse when dac was warm.
I will look at the reciver and maybe change it.
BR //Daniel
We tested the cable and source with another dac and there were no problem then.
Also it seams like the problem came/was worse when dac was warm.
I will look at the reciver and maybe change it.
BR //Daniel
Hello did you find solve the optical issue?
When you see the fault maybe you could use cool spray on the pcb to see if the fault go away?
Could you show schematic for avcc mod and IV / power supply??
Thanks
When you see the fault maybe you could use cool spray on the pcb to see if the fault go away?
Could you show schematic for avcc mod and IV / power supply??
Thanks
Hello,
I haven’t got time to look at it yet, but will try maybe tomorrow.
I was thinking of cold spray and if i can’t find the problem i will go and buy some.
I’m thinking of change the optical reciver to a TORX 147, have it at home.
Regarding the avcc i did it as in the post #3003. Didn’t change anything except for the capacitators at the output (10uF), i didnt have them at home but put a 3.3uf cheramic.
As for I/v stage i did like Victor in the 9018 thread. I will change it to a copy of the one in post #3003 when PCB arrive.
Chinese ES9018K2M I2S DAC
BR // Daniel
I haven’t got time to look at it yet, but will try maybe tomorrow.
I was thinking of cold spray and if i can’t find the problem i will go and buy some.
I’m thinking of change the optical reciver to a TORX 147, have it at home.
Regarding the avcc i did it as in the post #3003. Didn’t change anything except for the capacitators at the output (10uF), i didnt have them at home but put a 3.3uf cheramic.
As for I/v stage i did like Victor in the 9018 thread. I will change it to a copy of the one in post #3003 when PCB arrive.
Chinese ES9018K2M I2S DAC
BR // Daniel
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Daniel,
Presumably, you understood that the +3.3v label in Victor's schematic refers to the AVCC voltage for the dac channel that the output stage is attached to?
Also, ceramic caps at the AVCC output may not be such a good thing. Most are non-linear and they also tend to be piezoelectric. Might want to replace those when you get a chance.
Presumably, you understood that the +3.3v label in Victor's schematic refers to the AVCC voltage for the dac channel that the output stage is attached to?
Also, ceramic caps at the AVCC output may not be such a good thing. Most are non-linear and they also tend to be piezoelectric. Might want to replace those when you get a chance.
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Hi Mark,
Sorry, i linked to the wrong schematic. Link is corrected now and i build the schematic in post #151. So i have 1.65 v from avcc to outputstage.
I’m really happy with the sound if i manage to fix the lock problem when trying.
Regarding the cheramic caps at output for the avcc, what do you think is better? El-lyt? Film?
BR// Daniel
Sorry, i linked to the wrong schematic. Link is corrected now and i build the schematic in post #151. So i have 1.65 v from avcc to outputstage.
I’m really happy with the sound if i manage to fix the lock problem when trying.
Regarding the cheramic caps at output for the avcc, what do you think is better? El-lyt? Film?
BR// Daniel
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Regarding best type of AVCC output caps, I never decided. Also, it may depend on what opamps are being used and how they are powered. I know that bass may sound better if the AVCC opamps have a lot of local energy storage in close-by large electrolytics from the rail (or rails) to ground.
Another big sound quality improvement can be had by lowering DPLL Bandwidth as much as you can without encountering instability (loss of lock). (I doubt your optical SPDIF problem is related to the register setting, the board's MCU leaves it at default which is very tolerant of jitter IME).
Another big sound quality improvement can be had by lowering DPLL Bandwidth as much as you can without encountering instability (loss of lock). (I doubt your optical SPDIF problem is related to the register setting, the board's MCU leaves it at default which is very tolerant of jitter IME).