Markw4,
Tnx, I know the theory.
In my case, the dominating noise is ground noise of the 16-tap FIRDAC.
The reference noise is only a quoter of micro volt RMS in 20-20k.
I tried much noisier reference, filtered with RC 20k&22uF, the result was only a little worse, almost unnoticeable.
Sorry, сan’t answer with more details, being busy at work.
Tnx, I know the theory.
In my case, the dominating noise is ground noise of the 16-tap FIRDAC.
The reference noise is only a quoter of micro volt RMS in 20-20k.
I tried much noisier reference, filtered with RC 20k&22uF, the result was only a little worse, almost unnoticeable.
Sorry, сan’t answer with more details, being busy at work.
The entire DAC has been fitted into tiny 48-QFN Gowin Semiconductors GW1N-LV9QN48C6/15.
Maximal clock rate is 50MHz, no timing errors, it was lab-tested with Tang-nano 9k evaluation board.
It’s nice to have inexpensive second source for obsolete Spartan-6 FPGA.
Maximal clock rate is 50MHz, no timing errors, it was lab-tested with Tang-nano 9k evaluation board.
It’s nice to have inexpensive second source for obsolete Spartan-6 FPGA.
The problem is that ISE14.7 development tool for S6 is not properly supported.
I spent days tuning the software and hacking Windows 11 registry to make it somehow working.
Extended support means nothing, you have to use old Linux or WMware+Win7 or XP to run full featured ISE.
And it runs 10 times slower than Gowin development tools and no chance of supporting System Verilog and other things. Think twice before using S6 for the new development.
I spent days tuning the software and hacking Windows 11 registry to make it somehow working.
Extended support means nothing, you have to use old Linux or WMware+Win7 or XP to run full featured ISE.
And it runs 10 times slower than Gowin development tools and no chance of supporting System Verilog and other things. Think twice before using S6 for the new development.
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I'm not versed in fpga programming, but what seems to be the issue with spartan 7, as seeing it has better and updated dev toolkit? Price? Harder to program?
There isn't and it is no harder or easier to program than the Spartan 6 LX9 device used in the forum.
Pretty neat! I like it. Is toslink the only input and is it limited to 16 bit? I'd be down for a board
When using an FPGA as a discrete DAC, some hacking is required to use the cells efficiently. Such methods are not allowed in high-level systems like Vivado. It's similar to writing code in assembly rather than C. ISE 14.7 is an older system, so it will enable you to specify cell locations. ISE 14.7 is compatible only with Spartan-6 and some Artix-7 devices (e.g., xc7a100). It's a good idea to buy a used PC with Windows 7. For something like the xc6slx9, you can create the necessary files (mcs) in about 10 minutes. The xc7a100 is a much larger FPGA than the xc6slx9, so it takes a bit more time but less than an hour. I think ISE 14.7 is a DIY-friendly system.
Use REW. The results will be close match to AP555.
But first, you must have Cosmos-ISO ADC+APU and refresh your knowledge of Fourie Transform.
But first, you must have Cosmos-ISO ADC+APU and refresh your knowledge of Fourie Transform.