Charles,
When you have received the UcD180, I am really looking forward to your soundexperience of our Class-D amplifier
I like your comment where you show a good knowledge of feedback theory!
Regards,
Jan-Peter
www.hypex.nl
When you have received the UcD180, I am really looking forward to your soundexperience of our Class-D amplifier
I like your comment where you show a good knowledge of feedback theory!
Regards,
Jan-Peter
www.hypex.nl
Me too ! 🙂 🙂 🙂
I will use them in my active Manger system, which employs a phase_accurate subtractive crossover.
I am not that new to class-d amps, specially carrier-based ones. But I took a lot of wrong roads in the past.
It was only recently that I really sat down and used not only my imagination but maths combined with imagination in order to get nice feedback topologies. Suddenly a lot of possibilities for feedback networks popped up, all with feedback takeoff from the output filter. And they are not even that difficult to calculate !
But the UcD is a damn-clever circuit for it's simplicity. And for the cost of the modules it isn't even easy to get the parts in small quantities.
Regards
Charles
I'd like to learn more about the control theory, specifically the lead/lag relationships can anyone recommend a good link?
A good introduction into electronic control circuits can be found in
"Electronic Circuits" by Tietze & Schenk (i.e. the English version of "Halbleiterschaltungstechnik).
Maybe you will find it at a library. It is an expensive book and I wouldn't buy it for because of this chapter alone. I have only the German version unfortunately.
Regards
Charles
"Electronic Circuits" by Tietze & Schenk (i.e. the English version of "Halbleiterschaltungstechnik).
Maybe you will find it at a library. It is an expensive book and I wouldn't buy it for because of this chapter alone. I have only the German version unfortunately.
Regards
Charles
Hi,
Here's some updates I've been playing with.
I've upgraded the component selection on my differential version, which has of course made a significant improvement.
Graphs included of feedback shows tracking so well that you can't really see the ripple on it.
Results of this simulation at 1 volt input at 1khz:
DC component 6.4E-03
THD=0.29%
A worthy improvement of the part selection.
I also tried to implement another lag filter into the differential feedback loops, which seems to work well considering it needs optimising.
Results of this simulation at 1 volt 1khz:
DC component 5.9E-03
THD= 0.4%
Pic of circuit included as well.
Regards
Chris
Here's some updates I've been playing with.
I've upgraded the component selection on my differential version, which has of course made a significant improvement.
Graphs included of feedback shows tracking so well that you can't really see the ripple on it.
Results of this simulation at 1 volt input at 1khz:
DC component 6.4E-03
THD=0.29%
A worthy improvement of the part selection.
I also tried to implement another lag filter into the differential feedback loops, which seems to work well considering it needs optimising.
Results of this simulation at 1 volt 1khz:
DC component 5.9E-03
THD= 0.4%
Pic of circuit included as well.
Regards
Chris
Hello, guys.
I have a question: how does the basic UCD circuit perform at power off?
Imagine that, during the power off duration, the circuit can stop working properly because any oscillation condition is no longer met or some other cause, and the state remains so the lower mosfet is continuously on: that would produce a negative voltage transient in the speaker until the main rails disappear that could destroy the speaker.
How can we prevent this to happen? I am quite worried about that practical issue.
Other clock-based amps I have designed have logic for the disabling of the PWM and inverted PWM signals to the drive logic to avoid these problems.
Any comments on this issue?
Thanks!
I have a question: how does the basic UCD circuit perform at power off?
Imagine that, during the power off duration, the circuit can stop working properly because any oscillation condition is no longer met or some other cause, and the state remains so the lower mosfet is continuously on: that would produce a negative voltage transient in the speaker until the main rails disappear that could destroy the speaker.
How can we prevent this to happen? I am quite worried about that practical issue.
Other clock-based amps I have designed have logic for the disabling of the PWM and inverted PWM signals to the drive logic to avoid these problems.
Any comments on this issue?
Thanks!
Why would the amp want to switch to one rail if the other is removed? Decreasing (even to zero) one rail on an ideal UcD will simply place it in a clipped or nearly clipped state at zero output.
In a practical UcD there are also no mechanisms to produce such funny errors.
First I'd like to point out is that the amplifier is enabled/disabled simply by turning the comparator's tail current source on and off. This is controlled by normal power on/off timing circuitry like you'd always add anyway. This is the cleanest way of turning on and off.
It is good practice to do so. For power-on the upper driver needs to be precharged first. Otherwise, if for any reason (input offset) the first thing the amp tries is going high it will stall in a disabled state. Secondly, at clipping to positive you don't want the bootstrap cap to peter out, which means it's more like 100uF than 100nF. It needs to be precharged, because the bootstrap diode will fail if the output goes low with the bootstrap cap fully discharged.
The other point is that when the input signal is zero, no condition exists in which the amp would want to continuously turn on a FET.
If the positive rail disappeared, the emitter current of the input pair would cut out and the amp turn off. Until that happens, the amp is fully operational and won't do things the control loop doesn't allow.
When the negative rail is turned off, the driver supply or at least the "current mirror like" construction will call it quits. Again, operation simply ceases.
In a practical UcD there are also no mechanisms to produce such funny errors.
First I'd like to point out is that the amplifier is enabled/disabled simply by turning the comparator's tail current source on and off. This is controlled by normal power on/off timing circuitry like you'd always add anyway. This is the cleanest way of turning on and off.
It is good practice to do so. For power-on the upper driver needs to be precharged first. Otherwise, if for any reason (input offset) the first thing the amp tries is going high it will stall in a disabled state. Secondly, at clipping to positive you don't want the bootstrap cap to peter out, which means it's more like 100uF than 100nF. It needs to be precharged, because the bootstrap diode will fail if the output goes low with the bootstrap cap fully discharged.
The other point is that when the input signal is zero, no condition exists in which the amp would want to continuously turn on a FET.
If the positive rail disappeared, the emitter current of the input pair would cut out and the amp turn off. Until that happens, the amp is fully operational and won't do things the control loop doesn't allow.
When the negative rail is turned off, the driver supply or at least the "current mirror like" construction will call it quits. Again, operation simply ceases.
I meant during normal operation: when you switch the main supply off both rails start to slowly drop to zero due to the psu capacitors discharging.
I suppose that's because your comparator has double outputs, so when the bias current is turned off, both outputs go to 0 (or the off state).
I asked that because some of my designs (clocked or not clocked) generate a single pulse signal (PWM or whatever), and then, after level shifted, it is passed to a logic circuitry that produces the inverted version: that has the problem that always one of the signals is active, allowing one of the mosfets to be on. I suppose that it is better to do one of these things to disable the amp:
a) Disable both signals with additional logic or the SD pin if using am appropiate driver IC (IR2xxx, for example).
b) What if I force the upper control signal to "1"? Then the lower mosfet will be off and hence the upper one will stop working due to the lack of bootstrap pulsing. Do you think this will work?
Best regards
One thing more, Bruno.
For the overcurrent protection, you need to sense the output current, and then provide a way to disable the amp also.
Thanks for your explanations.
For the overcurrent protection, you need to sense the output current, and then provide a way to disable the amp also.
Thanks for your explanations.
You're confusing me.
If you want to disable a power stage like the UcD, turn off the current source. It can be legally used as a shutdown control.
Allowing the PSU to run out on a UcD circuit will not produce any damaging pulses. It will not be very clean either (a squeak and a pop). Use the current source to turn it off before that happens.
If you want to disable a power stage that uses an IC driver, use the SD pin if present or pull down the two inputs actively otherwise.
Turning on the upper fet and waiting till the driver goes to sleep is not a good idea for a self-oscillating amp of any sort. The bootstrap cap is sized in order to hold up long enough so a 20Hz clipped signal doesn't cause the gate voltage to drop too low. That's 25ms worth of full rail voltage on your output.
For a clocked amp, the bootstrap cap will still have hundreds of us worth of charge in it. Either case you will actually produce the effect you are trying to avoid.
The rule is simple. If your amp (or the device in which it is used) has a low-voltage supply in addition to the high power supply, you must actively detect removal of the AC line. The survival time of the HV supply is always much, much longer than that of the LV supply. You must stop operation before the LV supply starts falling. Depending of what exactly is powered by the LV supply the effects can be anywhere between annoying and catastrophic.
If you don't have a separate LV supply it is sufficient to provide an undervoltage lockout on both rails.
If you want to disable a power stage like the UcD, turn off the current source. It can be legally used as a shutdown control.
Allowing the PSU to run out on a UcD circuit will not produce any damaging pulses. It will not be very clean either (a squeak and a pop). Use the current source to turn it off before that happens.
If you want to disable a power stage that uses an IC driver, use the SD pin if present or pull down the two inputs actively otherwise.
Turning on the upper fet and waiting till the driver goes to sleep is not a good idea for a self-oscillating amp of any sort. The bootstrap cap is sized in order to hold up long enough so a 20Hz clipped signal doesn't cause the gate voltage to drop too low. That's 25ms worth of full rail voltage on your output.
For a clocked amp, the bootstrap cap will still have hundreds of us worth of charge in it. Either case you will actually produce the effect you are trying to avoid.
The rule is simple. If your amp (or the device in which it is used) has a low-voltage supply in addition to the high power supply, you must actively detect removal of the AC line. The survival time of the HV supply is always much, much longer than that of the LV supply. You must stop operation before the LV supply starts falling. Depending of what exactly is powered by the LV supply the effects can be anywhere between annoying and catastrophic.
If you don't have a separate LV supply it is sufficient to provide an undervoltage lockout on both rails.
For amps up to 10A output current you can use sense resistors between the rails and the fets, and a transistor to detect the voltage drop. The collectors of these go to the timer circuit that also handles on/off sequencing.
For higher currents, dissipation in the sense resistors becomes prohibitive and a sense winding on the inductor is more practical.
I hope neither scheme is considered as black art.
For higher currents, dissipation in the sense resistors becomes prohibitive and a sense winding on the inductor is more practical.
I hope neither scheme is considered as black art.
IMO that's one of the really sexy things about switching amps.
You only have to watch out for the amount of current, and not the SOA of the output devices as a function of output voltage and current like it is usually done with AB amps. The latter is one possible reason that some class AB amps struggle to drive "difficult" loads.
Almost all class-d amps I have heard so far had punchy and effortless bass reproduction. I have also heard other people saying the contrary. I think the class-d amps they were talking of simply had underdimensioned PSUs.
Regards
Charles
You only have to watch out for the amount of current, and not the SOA of the output devices as a function of output voltage and current like it is usually done with AB amps. The latter is one possible reason that some class AB amps struggle to drive "difficult" loads.
Almost all class-d amps I have heard so far had punchy and effortless bass reproduction. I have also heard other people saying the contrary. I think the class-d amps they were talking of simply had underdimensioned PSUs.
Regards
Charles
Charles,
i agree exactly about bass, no matter class A AB or D. IMHO, THD<.5%, and more damping factor (for car audio subwoofers especially, which have very small Vas and very heavy moving system and 1ohm impedance!) other questions to PSU.
Edited: But class D subamps much simpler vs AB even, because we can take cheap IR driver and fets and it works well at <100khz. PCB also can be designed fastly- requirements isn't so hard like >>100khz. Easy DIY class D reference design... UcD as subamp yet? However high freq. sound of this amp is really amazing for me.
i agree exactly about bass, no matter class A AB or D. IMHO, THD<.5%, and more damping factor (for car audio subwoofers especially, which have very small Vas and very heavy moving system and 1ohm impedance!) other questions to PSU.
Edited: But class D subamps much simpler vs AB even, because we can take cheap IR driver and fets and it works well at <100khz. PCB also can be designed fastly- requirements isn't so hard like >>100khz. Easy DIY class D reference design... UcD as subamp yet? However high freq. sound of this amp is really amazing for me.
I have a question regarding the 3b-variant I came up with earlier, effectively the double-loop topology.
If the connection from the outer loop filter to the comparator/output circuit is left out, the inner loop will oscillate by itself at some frequency. But when the outer loop is added, the oscillation frequency will move, depending on the LAG-filter and the outer feedback network.
I guess that the overall oscillation frequency will be where the total phase shifts in all these filters/parts sum up to 180 degrees. Am I correct?
If the connection from the outer loop filter to the comparator/output circuit is left out, the inner loop will oscillate by itself at some frequency. But when the outer loop is added, the oscillation frequency will move, depending on the LAG-filter and the outer feedback network.
I guess that the overall oscillation frequency will be where the total phase shifts in all these filters/parts sum up to 180 degrees. Am I correct?
If my assumption is correct, I don't quite understand in what way the requirements on the OP are alleviated???
You are correct in equally bold print.
The point is that the lead network (the one that works at HF) is passive and does not pass through the opamp. Thus, delay from the op amp cannot affect that part.
The point is that the lead network (the one that works at HF) is passive and does not pass through the opamp. Thus, delay from the op amp cannot affect that part.
Ok, thank you very much for verifying my assumption. (Double-loops weren't covered that deeply in the classes I took on control theory and electronicsBruno Putzeys said:
.)All this aside, I feel that complex topologies perhaps are better left as advanced excercises, and that we should focus on simple-and-robust for the UcD-clone DIY design. With this in mind, I indend to begin drafting a pcb layout this weekend, and I will try to cover as many aspects as possible of those that have been discussed in this thread so far. I cannot promise a fully differential input stage plus differential output etc., but I will certainly give it a try. The main point should be to make something that is relatively simple to get going for someone not very experienced with class D, and all bells & whistles beyond that should be considered as bonuses.
If that's not good enough, I invite others to help with the pcb work; I'm open to suggestions...
Hi,
I'll be posting an updated circuit, graphs, screenshot, and the pspice *.DSN file this time as well, if you're interested. Simulations seem to show it's a worthy improvement in DC offset alone, I wonder what this would do for psrr as well.
There was an error in the previous one I had overlooked entirely, surprised no one mentioned anything.
Expect update shortly I'm just finishing up with it now.
I'll be posting an updated circuit, graphs, screenshot, and the pspice *.DSN file this time as well, if you're interested. Simulations seem to show it's a worthy improvement in DC offset alone, I wonder what this would do for psrr as well.
There was an error in the previous one I had overlooked entirely, surprised no one mentioned anything.
Expect update shortly I'm just finishing up with it now.
Yes, I'm interested!classd4sure said:
I haven't really gotten anywhere with the PCB yet; it took a fair amount of time just to re-read all 30 pages of this threadclassd4sure said:
. (To collect and sort through all the ideas and suggestions made so far...)I wonder what the best way is to take output from the comparator to those two extra drivers (for a bridge version)? I suspect something has to be added to create extra outputs???
johanps said:
Yes, I'm interested!
I haven't really gotten anywhere with the PCB yet; it took a fair amount of time just to re-read all 30 pages of this thread
I wonder what the best way is to take output from the comparator to those two extra drivers (for a bridge version)? I suspect something has to be added to create extra outputs???
Hi,
Good news..Bad news. I wanted to have those files I mentioned posted yesterday, but what happened while I was finishing up with it, Orcad decided it didn't like my circuit, flagged the file as "bad", locked it up and threw away the key!!! I wasn't able to open it anymore, kept telling me I ran out of memory. The bad news is, I remade it. 😀
I still have the second integrator/lag network in it, with non optimised values. Playing around with them achieved simulations with THD of 0.19%, one of the lowest I've been able to simulate thus far, and a rather impressive DC offset of 4.5E-05. So I think with proper tuning it could prove to be a decent circuit. DC offset seems to change with filter values however it's nice and acceptably low with any value, usually in the range of a few millivolts at most, some just bring it lower than others.
It uses 1 feedback loop for a half bridge, for full bridge simply add another to the second op amp exactly like the first one has, up to a new lag network after the other side of the filter, I would think. I redid it with "symmetrical" in mind.
You should have little trouble ripping out the second integrator to convert it to a more straightforward feedback loop.
It is capable of making full power with just 1 volt input.
Of course the mosfets being irf540's are just there to simulate with, the dual spikes that you see on most of PWM peaks are from the shoot through, which I believe better mosfet selection will take care of as discussed before.
It seems to simulate half decent just by ripping out the extra RC networks of the feedback loop, and that retains the ability of going full bridge and making it fully differential all the way through. Looked like it needed some optimising though, the waves look alot nicer with the added integrator.
As far as taking output from the comparator goes Bruno mentioned it in one of these threads, Thought it was this one, but as you say it's so long..I'm always going back in it for more info that I know is there and can't find it. So simple it would be a shame not to provide the option, simply hang another transistor pair off of the current mirror exactly like the ones already there!! Nice huh? I had simulated that before rather well in trying to make it full bridge, but I didn't have the circuit then that I do have now.
Time for a coffee, I will be sending those files rather shortly this time. Stay tunned.
Chris
- Status
- Not open for further replies.