Behold!!.. nah just jokin.
So here it is, my updated version.. back from the great beyond of lost bytes. I played around with it, changed a few glaring mistakes.. I hope there aren't (many) more.
Feedback is most welcome.
This circuit works for alot higher voltages unlike my last one where I think the feedback/input would start clipping long before full gain was ever reached.
With the values given full power is reached at just over a volt input, this can be easily adjusted by the values of the series input resistors.
I took out all my added libraries from the project and there's no exotic parts used so it should work for everyone I hope.
If anyone feels it's worthy and decides to optimise the feedback network properly I'd be interested in knowing about it! I haven't yet looked at gain/phase so.. I see no reason in making anyone wait while I attempt to struggle with that.
Once again, to convert feedback to fully differential for a full bridge application, just mirror the existing one.
I'm sure it could do better with a better choice of mosfet, but if you're thinking that the IRF540 has become my standard for simulating with, I think you're right, at least until I take the time to find a better one.
The spikes on both sides of the square wave form I believe are caused by shoot through..Could be snubbered but I'd rather find a better mosfet first so I left that out.
By the way I got my samples from Fairchild in 🙂 You'd really think they'd prefer to sell them in bulk to a supplier who could part them out cheaper and still make profit, considering they sent it pre paid FedEx from Malaysia, maybe they use it as a tax write off? "Ain't nuthin free"
Enjoy,
Chris
So here it is, my updated version.. back from the great beyond of lost bytes. I played around with it, changed a few glaring mistakes.. I hope there aren't (many) more.
Feedback is most welcome.
This circuit works for alot higher voltages unlike my last one where I think the feedback/input would start clipping long before full gain was ever reached.
With the values given full power is reached at just over a volt input, this can be easily adjusted by the values of the series input resistors.
I took out all my added libraries from the project and there's no exotic parts used so it should work for everyone I hope.
If anyone feels it's worthy and decides to optimise the feedback network properly I'd be interested in knowing about it! I haven't yet looked at gain/phase so.. I see no reason in making anyone wait while I attempt to struggle with that.
Once again, to convert feedback to fully differential for a full bridge application, just mirror the existing one.
I'm sure it could do better with a better choice of mosfet, but if you're thinking that the IRF540 has become my standard for simulating with, I think you're right, at least until I take the time to find a better one.
The spikes on both sides of the square wave form I believe are caused by shoot through..Could be snubbered but I'd rather find a better mosfet first so I left that out.
By the way I got my samples from Fairchild in 🙂 You'd really think they'd prefer to sell them in bulk to a supplier who could part them out cheaper and still make profit, considering they sent it pre paid FedEx from Malaysia, maybe they use it as a tax write off? "Ain't nuthin free"
Enjoy,
Chris
Hi Chris, and thanks for the .DSN-file; now I could finally see what you were up to 🙂.
Although this looks very nicely differential, I think you should be able to do diff inputs with just one OP. In the circuit you posted, the two OPs drive the comparator differentially, which looks nice, but I don't get the point?!? I'm guessing you did it this way because of what Bruno posted earlier (see continuation below)...
What I want to figure out is how to get extra outputs from the comparator (this has escaped me so far); then for the bridge version, you only add two drivers+mosfets+filter, and feed back from that inverted output to the differential input at the OP.
I could be wrong about this, but that's how I envision it at the moment at least...
Regards / Johan
Although this looks very nicely differential, I think you should be able to do diff inputs with just one OP. In the circuit you posted, the two OPs drive the comparator differentially, which looks nice, but I don't get the point?!? I'm guessing you did it this way because of what Bruno posted earlier (see continuation below)...
This is true, and/but refers to a loop where the OP is not part of the control loop. In your/our case, it is, and assuming the OP has its own regulated supplies (which it must have if the HV supply is more than +/-18V), then we get all the CMRR we need anyway.Bruno Putzeys said:
Hmm, I may be misunderstanding you here; do you mean "use two independent loops/amplifiers for the inverting and non-inverting paths of the amplifier"? If so, I respectfully disagree. (Then you would get two independently oscillating loops, which only leads to a world of hurt.)classd4sure said:
What I want to figure out is how to get extra outputs from the comparator (this has escaped me so far); then for the bridge version, you only add two drivers+mosfets+filter, and feed back from that inverted output to the differential input at the OP.
I could be wrong about this, but that's how I envision it at the moment at least...
Regards / Johan
Hi,
You can, but it's then not a fully balanced input, that's more or less considered to be "fake" differential inputs, having no real benefits the fully balanced input provides.
Two op amps are certainly the way to go, they aren't that expensive and it doesn't add much complication to it worth mentioning either.
Not if you only use one amp you don't, there'd be no common mode. PSRR would suffer as well. I'm sure mixing the feedback with the reference right at the input might not be the prefered way to go, but it saves more op amps if you want to go with a second lag network, and seems to work just fine. If you want a more proper circuit take the feedback loop out of the diff input stage and add yet two more op amps.
That's what I meant yes, fully differential circuit. How else can you take feedback for a full bridge? I don't think you wind up with two oscillating loops, there's still but one comparator after all, perhaps it would be accurate to term it as being a differential oscillating loop? I really dont' see how, or why that would cause any problems.
While I'm sure it's not ideal, I'm not convinced it's a bad idea. Actually I think we're talking about the same circuit, only my version is fully balanced/differential, and I dont' see that being a bad thing at all. I might try to get a full bridge version simulated today. It won't be hard with what I've done already. Thanks for your feedback.
Chris
You can, but it's then not a fully balanced input, that's more or less considered to be "fake" differential inputs, having no real benefits the fully balanced input provides.
Two op amps are certainly the way to go, they aren't that expensive and it doesn't add much complication to it worth mentioning either.
Not if you only use one amp you don't, there'd be no common mode. PSRR would suffer as well. I'm sure mixing the feedback with the reference right at the input might not be the prefered way to go, but it saves more op amps if you want to go with a second lag network, and seems to work just fine. If you want a more proper circuit take the feedback loop out of the diff input stage and add yet two more op amps.
That's what I meant yes, fully differential circuit. How else can you take feedback for a full bridge? I don't think you wind up with two oscillating loops, there's still but one comparator after all, perhaps it would be accurate to term it as being a differential oscillating loop? I really dont' see how, or why that would cause any problems.
While I'm sure it's not ideal, I'm not convinced it's a bad idea. Actually I think we're talking about the same circuit, only my version is fully balanced/differential, and I dont' see that being a bad thing at all. I might try to get a full bridge version simulated today. It won't be hard with what I've done already. Thanks for your feedback.
Chris
Hi All!
Chris,
Are you sure that your circuit is working. I redrawed it in OrCAD9.1 and it makes the attached result for a 1V amplitude 1kHz sinus signal. Could you imagine what is the problem between the 0.700msec and 1msec????
The attached pdf contains the circuit diagram and the simulation results...
Thanks, lkadar.
EDIT: Why is my attachement disappeared????
Chris,
Are you sure that your circuit is working. I redrawed it in OrCAD9.1 and it makes the attached result for a 1V amplitude 1kHz sinus signal. Could you imagine what is the problem between the 0.700msec and 1msec????
The attached pdf contains the circuit diagram and the simulation results...
Thanks, lkadar.
EDIT: Why is my attachement disappeared????
Hi Lkadar, welcome to the thread.
I'm sure it's working, I'm also sure not all the values are correct, it needs optimising.
I think what you're probably refering to is the increase in ripple you see during certain parts of the waveform?
The waveforms I posted were for a 20Khz signal, at 1Khz (I just checked) the output gets alot more ripple on it towards the peaks doesn't it, I think there's a huge step in modulation frequency which just goes to show how bad those second lag network values are.
I'm glad you got it working anyway, I realised late last night you couldn't just run my design because it opens in orcad but without Pspice, I recommend simply creating your own project in orcad, then opening the design file I posted, and just copy and paste it into your new project, that should get it working with pspice with less time and effort, then you can spend more of that time/effort playing with the values. 😀
If indeed you were talking about what I think you were, try changing the values of the two capacitors inside the op amps' feedback loop to 50n and that will clean it right up. Once again they aren't the right values, but that seems to work a bit better and hopefully give you a nicer demonstration of it.
I will try to optimise to find the correct values using Bode plots, but I'm not entirely sure how, still looking for decent information on it without having to spend 200$ on a book that might not explain it well.
I'll include a screenshot of it with that value changed to 50n, for both 1khz and 20khz. You can see with these values there's still some gain over the audio band which isn't great, again, just goes to show they're the wrong values.
Thanks for your question, it was a fair one.
Regards,
Chris
I'm sure it's working, I'm also sure not all the values are correct, it needs optimising.
I think what you're probably refering to is the increase in ripple you see during certain parts of the waveform?
The waveforms I posted were for a 20Khz signal, at 1Khz (I just checked) the output gets alot more ripple on it towards the peaks doesn't it, I think there's a huge step in modulation frequency which just goes to show how bad those second lag network values are.
I'm glad you got it working anyway, I realised late last night you couldn't just run my design because it opens in orcad but without Pspice, I recommend simply creating your own project in orcad, then opening the design file I posted, and just copy and paste it into your new project, that should get it working with pspice with less time and effort, then you can spend more of that time/effort playing with the values. 😀
If indeed you were talking about what I think you were, try changing the values of the two capacitors inside the op amps' feedback loop to 50n and that will clean it right up. Once again they aren't the right values, but that seems to work a bit better and hopefully give you a nicer demonstration of it.
I will try to optimise to find the correct values using Bode plots, but I'm not entirely sure how, still looking for decent information on it without having to spend 200$ on a book that might not explain it well.
I'll include a screenshot of it with that value changed to 50n, for both 1khz and 20khz. You can see with these values there's still some gain over the audio band which isn't great, again, just goes to show they're the wrong values.
Thanks for your question, it was a fair one.
Regards,
Chris
Hi All!
I found the problem. It caused by the fact that the opamps are overdriven. I replaced the 20k resistors by 4.7k ones in the feedback and now it works well. THD @20kHz-1V -> 0.636%, DC-component -> 4.757mV, oscillation frequency ~400kHz.
Best regards, lkadar.
EDIT: Chris, I've just read your post (after I wrote this...), many thanks for your reply...
I found the problem. It caused by the fact that the opamps are overdriven. I replaced the 20k resistors by 4.7k ones in the feedback and now it works well. THD @20kHz-1V -> 0.636%, DC-component -> 4.757mV, oscillation frequency ~400kHz.
Best regards, lkadar.
EDIT: Chris, I've just read your post (after I wrote this...), many thanks for your reply...
lkadar said:
You're welcome, and thank you. 4.7k is the value I originally used, 20K brought DC offset down to insane levels (4.5E-05), but yeah, those are the values that need changing. Results look nice with 4.7k at both 1khz and 20khz, and DC offset is most respectable. This is why I'd really like to see how good it would work with actual correct values given the gain/phase, as it seems to have some potential even with the wrong values.
Ok, thanks for the clarification - as long as we're talking one comparator ("one oscillation loop"), it's cool 😎.classd4sure said:
I'd be interested in seeing your full-bridge circuit when you get it done!
Regards / Johan
johanps said:
Possibly tonight, or tomorrow I think. Right now I'm still playing around with values for my feedback network, just changing to 4.7k isn't good enough, actual Fs is more like 800khz (you spot it easiest with a low input voltage).
I'd also be interested in seeing your version of a full bridge 🙂
That said...
Just double up the output transistors of the comparator. Stick em in there right beside the others = 4 floating outputs. Then it's just a matter of doubling up everything after that point (drivers etc). The filter will have to change somewhat, also adding a coupling cap between the two filter halves.
Regards,
Chris
PS: I just ran one sim with input voltage of 0.1volt at 1khz=
DC COMPONENT = 2.208626E-03
TOTAL HARMONIC DISTORTION = 1.984740E-01 PERCENT
Fs is centered on 640Khz though.. I'll try a few more
Hi,
........And a new dawn hath risen 😉
Ahhhhhhhhh, I feel GOOD!!
So yeah I made ....changes 🙂
It's nice to know Pspice can do it....or...is it?
1 volt input 100W output at 20khz 4 harmonics
DC COMPONENT = 1.833048E-02
TOTAL HARMONIC DISTORTION = 3.606490E-02 PERCENT
Woooooohoooooooooooo......Goodnight!
........And a new dawn hath risen 😉
Ahhhhhhhhh, I feel GOOD!!
So yeah I made ....changes 🙂
It's nice to know Pspice can do it....or...is it?
1 volt input 100W output at 20khz 4 harmonics
DC COMPONENT = 1.833048E-02
TOTAL HARMONIC DISTORTION = 3.606490E-02 PERCENT
Woooooohoooooooooooo......Goodnight!
classd4sure said:
Hi All!
Wooooooow, it's nice... Could you just send your last schematic if you are not sleeping yet?
Regards, lkadar.
Hi,
Sleep? During robot wars? pshaaw....crazy talk.
It's still a work in progress, I can tell you it's been simplified somewhat, stuck to basics, nothing creative this time. Aside from that, tuning other values in the circuit made a difference of night and day.
I was just thrilled to see a new barrier broken on the old THD scale, and by a significant amount at that. Does it hold for other frequencies?
0.1 volt input 1W output at 20khz 4 harmonics
DC COMPONENT = 1.841969E-02
TOTAL HARMONIC DISTORTION = 2.043326E-01 PERCENT
1V input, 100W output, 1khz 5 harmonics
DC COMPONENT = 8.831758E-03
TOTAL HARMONIC DISTORTION = 1.911358E-01 PERCENT
Waiting on more results. Fs ~ 500Khz which is nice.
I find it curious THD is lowest at full power and max frequency, really you'd think it would be opposite ..and it should be.
When I'm done I'll pass it along, however good or bad it may be.
Regards,
Chris
Sleep? During robot wars? pshaaw....crazy talk.
It's still a work in progress, I can tell you it's been simplified somewhat, stuck to basics, nothing creative this time. Aside from that, tuning other values in the circuit made a difference of night and day.
I was just thrilled to see a new barrier broken on the old THD scale, and by a significant amount at that. Does it hold for other frequencies?
0.1 volt input 1W output at 20khz 4 harmonics
DC COMPONENT = 1.841969E-02
TOTAL HARMONIC DISTORTION = 2.043326E-01 PERCENT
1V input, 100W output, 1khz 5 harmonics
DC COMPONENT = 8.831758E-03
TOTAL HARMONIC DISTORTION = 1.911358E-01 PERCENT
Waiting on more results. Fs ~ 500Khz which is nice.
I find it curious THD is lowest at full power and max frequency, really you'd think it would be opposite ..and it should be.
When I'm done I'll pass it along, however good or bad it may be.
Regards,
Chris
Hi,
Finished the sims and too burnt to make heads or tails out of it anymore, seems to be mixed results, but all are better than previous circuits performed, which I've posted anyway.
No "ideal" parts either, still with old faithfulls (irf540) and bad shoot through, I think I now have reason to hunt down a working model of a better switch.
Anyway, in the meantime why not try playing around with the one you've got there? Better yet use it as a base and try a few of your own variations, I'd like to see more circuits from more people, might get some good ideas that way.
Here's the results from my last sim (plus the others):
1 volt input 100W output at 20khz 4 harmonics
DC COMPONENT = 1.833048E-02
TOTAL HARMONIC DISTORTION = 3.606490E-02 PERCENT
_____________________________________________________
0.1 volt input 1W output at 20khz 4 harmonics
DC COMPONENT = 1.841969E-02
TOTAL HARMONIC DISTORTION = 2.043326E-01 PERCENT
Fs=640khz
____________
1volt 100W 1khz 5 harmonics
DC COMPONENT = 8.831758E-03
TOTAL HARMONIC DISTORTION = 1.911358E-01 PERCENT
Fs= centered on 500khz, starts at 300khz goes up to 680k
_____________
.1 volt 1W 1khz 5 harmonics
DC COMPONENT = 1.869217E-02
TOTAL HARMONIC DISTORTION = 6.220785E-02 PERCENT
Fs~640khz
Rest assured, I will post it in a day or two.
Regards,
Chris
Finished the sims and too burnt to make heads or tails out of it anymore, seems to be mixed results, but all are better than previous circuits performed, which I've posted anyway.
No "ideal" parts either, still with old faithfulls (irf540) and bad shoot through, I think I now have reason to hunt down a working model of a better switch.
Anyway, in the meantime why not try playing around with the one you've got there? Better yet use it as a base and try a few of your own variations, I'd like to see more circuits from more people, might get some good ideas that way.
Here's the results from my last sim (plus the others):
1 volt input 100W output at 20khz 4 harmonics
DC COMPONENT = 1.833048E-02
TOTAL HARMONIC DISTORTION = 3.606490E-02 PERCENT
_____________________________________________________
0.1 volt input 1W output at 20khz 4 harmonics
DC COMPONENT = 1.841969E-02
TOTAL HARMONIC DISTORTION = 2.043326E-01 PERCENT
Fs=640khz
____________
1volt 100W 1khz 5 harmonics
DC COMPONENT = 8.831758E-03
TOTAL HARMONIC DISTORTION = 1.911358E-01 PERCENT
Fs= centered on 500khz, starts at 300khz goes up to 680k
_____________
.1 volt 1W 1khz 5 harmonics
DC COMPONENT = 1.869217E-02
TOTAL HARMONIC DISTORTION = 6.220785E-02 PERCENT
Fs~640khz
Rest assured, I will post it in a day or two.
Regards,
Chris
Are you sure it IS shoot-through and not diode reverse-recovery, though I'm not sure if and how simulators deal with that at all. If yes, it would be helpful to add a better anti-parallel diode.
Regards
Charles
Reverse recovery is extremely badly modelled in simulators, usually not at all. Simulations on switching circuits involving pn junctions are therefore to be taken with a grain of salt.
If the power stage has shoot-through in idling conditions, it is real shoot through. Diode recovery only happens when it has been forward-biased before.
This happens when the LF ouput current exceeds the triangular "bias" current that flows in the filter. When the sign of the inductor current no longer periodically reverses, hard switching occurs. Depending on the magnitude of the current, the body diode will have been in conduction during the dead time or even during the full cycle (=when the voltage drop across Ron exceeds 1Vf).
If the power stage has shoot-through in idling conditions, it is real shoot through. Diode recovery only happens when it has been forward-biased before.
This happens when the LF ouput current exceeds the triangular "bias" current that flows in the filter. When the sign of the inductor current no longer periodically reverses, hard switching occurs. Depending on the magnitude of the current, the body diode will have been in conduction during the dead time or even during the full cycle (=when the voltage drop across Ron exceeds 1Vf).
Hello,
All I can tell you at the moment is that it doesnt' occur at all during zero crossing of the signals, and seems to grow larger respect to the amplitude of the output.
When it is there, I see dual spikes on the tops of the square wave, one on each side, these spikes also carry through to the inverting and non inverting input..but not enough to cause it to switch on it's own.
I certainly am taking mosfet models with a grain of salt to say the least, however I think they should do a fair job of at least modeling the gate charge ratio, so I thought it couldn't hurt to give that a try.
Woulnd't hurt to give the anti parallel diode a quick try either! I know adding dead time does nothing at all to help it, or diminish it, which is why I was leaning towards "gate step". Bruno's explanation seems to describe it though, I'll have to read it again after I've had some sleep, about to fall on my face.
Many thanks,
Chris
All I can tell you at the moment is that it doesnt' occur at all during zero crossing of the signals, and seems to grow larger respect to the amplitude of the output.
When it is there, I see dual spikes on the tops of the square wave, one on each side, these spikes also carry through to the inverting and non inverting input..but not enough to cause it to switch on it's own.
I certainly am taking mosfet models with a grain of salt to say the least, however I think they should do a fair job of at least modeling the gate charge ratio, so I thought it couldn't hurt to give that a try.
Woulnd't hurt to give the anti parallel diode a quick try either! I know adding dead time does nothing at all to help it, or diminish it, which is why I was leaning towards "gate step". Bruno's explanation seems to describe it though, I'll have to read it again after I've had some sleep, about to fall on my face.
Many thanks,
Chris
Hi,
That describes it exactly, I was wondering why it only occured at + or - output and not at idle, it gets remarkably worse with increasing amplitude.
So, since there seems to be no hard fast rule of thumb or anything on how to avoid this, would it then be considered good practice to simply include the anti parallel diode into the design, or just keep trying mosfet after mosfet until one finally does a decent job of it. Are there any reasons who I shouldn't use an anti parallel diode?
Thanks,
Chris
Bruno Putzeys said:
That describes it exactly, I was wondering why it only occured at + or - output and not at idle, it gets remarkably worse with increasing amplitude.
So, since there seems to be no hard fast rule of thumb or anything on how to avoid this, would it then be considered good practice to simply include the anti parallel diode into the design, or just keep trying mosfet after mosfet until one finally does a decent job of it. Are there any reasons who I shouldn't use an anti parallel diode?
Thanks,
Chris
Here's a PCB starting point
Hi everyone!
Here is an attempt at a starting point for the ucd-clone PCB, made with Eagle 4.11. I haven't routed any tracks yet; I just want input on things to do/not to do on a component-placement-level.
Let me explain some of the thoughts that have gone into this:
* The PCB is inteded to be 80x100mm for one channel (conveniently corresponding to the size allowed by the free version of Eagle). However, I have only drawn one output section, leaving enough space to mirror that for a full bridge option. (The single-ended version fits on 80x70mm) (The mosfets on the right are intended to be mounted standing up.)
* The input/comparator can/will have separate ground planes from the output stage(s). Thus, power supply+ground connections are correspondingly separated.
* For input/output connectors, I've used simple pin-heads - these are the most universal I can think of, and/or one may substitute them for soldering wires directly onto the board.
* There's an optional "enable" signal, which when pulled actively low will enable the comparator's operation. This funciton is possible to leave out by omitting Q12+R15, and shorting over collector/emitter pins where Q12 would have been.
* There's an optional "Output+12" input, which is for pre-charging before pulling down "enable". External pre-charing can be left out, and replaced with the optional charge circuit R16+D8.
* The PCB should allow many different configurations to be built; basic UCD, differential input UCD, UCD with bridge output, UcD with LAG-filter and single-ended output, etc...
That's why I intend to leave some connections from feedback networks to inputs for air-wire "configuration".
* Room is made for a 8-pin OP, which could house a single or dual OP, for whatever needs the builder desires.
As you see, the basic PCB design might supply lots of options; it's intended that one takes the source schematic file and tailor it to ones needs (by removing superflous stuff, and/or making missing connections) before manufacturing.
Alternatively, we could simply document one or two basic "profiles" of simple builds on the basic PCB as it is (or rather: will be).
Constructive feedback will be appreciated (but don't start that "hole-mounted is a waste of time" debate 🙂)
Oh, by the way, there's one SMD component in this design; a decoupling cap under the IC 😉.
Hi everyone!
Here is an attempt at a starting point for the ucd-clone PCB, made with Eagle 4.11. I haven't routed any tracks yet; I just want input on things to do/not to do on a component-placement-level.
Let me explain some of the thoughts that have gone into this:
* The PCB is inteded to be 80x100mm for one channel (conveniently corresponding to the size allowed by the free version of Eagle). However, I have only drawn one output section, leaving enough space to mirror that for a full bridge option. (The single-ended version fits on 80x70mm) (The mosfets on the right are intended to be mounted standing up.)
* The input/comparator can/will have separate ground planes from the output stage(s). Thus, power supply+ground connections are correspondingly separated.
* For input/output connectors, I've used simple pin-heads - these are the most universal I can think of, and/or one may substitute them for soldering wires directly onto the board.
* There's an optional "enable" signal, which when pulled actively low will enable the comparator's operation. This funciton is possible to leave out by omitting Q12+R15, and shorting over collector/emitter pins where Q12 would have been.
* There's an optional "Output+12" input, which is for pre-charging before pulling down "enable". External pre-charing can be left out, and replaced with the optional charge circuit R16+D8.
* The PCB should allow many different configurations to be built; basic UCD, differential input UCD, UCD with bridge output, UcD with LAG-filter and single-ended output, etc...
That's why I intend to leave some connections from feedback networks to inputs for air-wire "configuration".
* Room is made for a 8-pin OP, which could house a single or dual OP, for whatever needs the builder desires.
As you see, the basic PCB design might supply lots of options; it's intended that one takes the source schematic file and tailor it to ones needs (by removing superflous stuff, and/or making missing connections) before manufacturing.
Alternatively, we could simply document one or two basic "profiles" of simple builds on the basic PCB as it is (or rather: will be).
Constructive feedback will be appreciated (but don't start that "hole-mounted is a waste of time" debate 🙂)
Oh, by the way, there's one SMD component in this design; a decoupling cap under the IC 😉.
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