Interesting read. I'll admit I'm not yet into transformers (not even tubes
). But this may be a good resource: http://www.analog.com/static/imported-files/application_notes/AN_912.pdf
). But this may be a good resource: http://www.analog.com/static/imported-files/application_notes/AN_912.pdf
Hi AR2,
in the PDF you attached in the post #180 there is a very crude mistake - cap. multipliers with BC516/BC517 have short circuit between input and the base of input darlington which is a straight path for ripple and noise. Made that way the circuit presents almost all of the ripple and noise into the output of the cap. multiplier - there is no PSRR i.e. the circuit is useless.
If you want to make it right (PSRR about 60 dB) it should look like this (one darlington per rail is enough):
in the PDF you attached in the post #180 there is a very crude mistake - cap. multipliers with BC516/BC517 have short circuit between input and the base of input darlington which is a straight path for ripple and noise. Made that way the circuit presents almost all of the ripple and noise into the output of the cap. multiplier - there is no PSRR i.e. the circuit is useless.
If you want to make it right (PSRR about 60 dB) it should look like this (one darlington per rail is enough):
Attachments
what's few db's between friends .........
there is pretty good SNR ratio already before these cap multi's
anyway - take it as usual ZM's approach - drawn on back of napkin in early hours , and open source for friendly criticize .......
so - AR2 - just change first 470R resistor to bigger - 2K2 or even bigger ..... so even my friend Juma will be happy
btw. first darlington is just double diode
Zero or sixty - yes, that's a few
what's few db's between friends .........
It's not the solution - as long as there is a short circuit between input and first 330R resistor.
first darlington is **** - just take it out and adopt the circuit to sch. in post #184
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Those two sch. are not equivalent, a big difference is that first sch. puts almost all the ripple and hum to the base of the second darlington rendering it useless.
I'm telling you this 'cause it looked strange to me so I made a quick mock-up and with 200mV ripple at input (40mA through the load) I got 150mV ripple at the output.
With circuit from post #184 I had to increase ripple to 1V in order to measure 1mV ripple at the output (same 40mA load).
Mistakes like that happen all the time - we all sometimes do something wrong and if there are no immediate penalties bad praxis continues to live...
I just thought to mention it so it can be avoided next time
I'm telling you this 'cause it looked strange to me so I made a quick mock-up and with 200mV ripple at input (40mA through the load) I got 150mV ripple at the output.
With circuit from post #184 I had to increase ripple to 1V in order to measure 1mV ripple at the output (same 40mA load).
Mistakes like that happen all the time - we all sometimes do something wrong and if there are no immediate penalties bad praxis continues to live...
I just thought to mention it so it can be avoided next time
you're right with analysis ;
in first glance I reckon that you saw some mistake in topology ( in fact pretty often thing on my napkin drawings ) , but now I realize that you thought about values strictly .
anyway - my intention was , considering that this cap multi is placed after stacked LM reg , not to make broadband cap multi , but to improve higher frequency filtering of preceding stage ;
so - I wasn't trying to improve RR , which is already excellent on input of CM ( taking that strictly from engineering point of view ) , but to make local decoupling for higher freq garbage .
in first glance I reckon that you saw some mistake in topology ( in fact pretty often thing on my napkin drawings
) , but now I realize that you thought about values strictly .anyway - my intention was , considering that this cap multi is placed after stacked LM reg , not to make broadband cap multi , but to improve higher frequency filtering of preceding stage ;
so - I wasn't trying to improve RR , which is already excellent on input of CM ( taking that strictly from engineering point of view ) , but to make local decoupling for higher freq garbage .
Speaking of PCB fabrication, I'm doing a layout for a new DAC that will be part of my music streaming systems placed around the house. I wanted low power consumption that I could leave on all the time, so I'm using a 2022 based tripath amp being driven by an airport express. I'm building these DACs for better sound from the AE. The DAC design uses a pair of Lundahl LL1690's on the output, so it's germane to this thread (I started a new thread about it, but I'm just getting crickets).
I'm going to have some boards made and if anybody would like to go in on some, I'll adjust my order accordingly.
The other thread is here:
http://www.diyaudio.com/forums/digi...-yet-another-crystal-dac-lundahl-outputs.html
I'm going to have some boards made and if anybody would like to go in on some, I'll adjust my order accordingly.
The other thread is here:
http://www.diyaudio.com/forums/digi...-yet-another-crystal-dac-lundahl-outputs.html
o'scope screen picture: Lundahl LL1690 on Buffalo (ES9008) DAC with 8.9Ω load
Is that a nice square wave? 1kHz with 8.9kΩ load (pot before preamp) across secondaries, no resistor(s) on primaries.
Connection diagram:
An externally hosted image should be here but it was not working when we last tested it.
Is that a nice square wave? 1kHz with 8.9kΩ load (pot before preamp) across secondaries, no resistor(s) on primaries.
Connection diagram:
An externally hosted image should be here but it was not working when we last tested it.
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