The output voltage from the CF op-amp is the product of the current flowing out of the - terminal and the internal Zt impedance. As this output voltage is ultimately derived from a current, then the buffer stage (from the maths analysis point of view) can be considered a transimpedance amplifier.
The 'inverting' node of a 'CF' arrangement is, in fact, merely the emitter of a transistor arranged in the familiar common-emitter configuration, with voltage stimulus applied to its base-the 'non-inverting' node.
This transistor, therefore, is a differential amplifier, and effectively amplifies the difference between its base and emitter voltages.
Essentially, the resulting error voltage is multiplied by the transistor's transconductance, giving an incremental output voltage that is a function of the magnitude of this transistor's collector load.
No transimpedance involved.
Moreover, with so-called 'current feedback', the feedback network's component values are deliberately chosen so that they constitute a significant load on the first stage.
This means that local first stage gain varies as you vary your feedback resistors......(Remember local gain of simple common emitter stage~Rc/Re???)
Therefore, for low closed loop gains, the Thevenin resistance at the feedback summing node must necessarily increase, since the reduction in closed loop gain is facilitated by increasing the value of the grounded resistor in the feedback network.
Consequently local first stage gain is reduced, which must perforce be accompanied by a reduction in foward path gain.
This then is the mechanism by which bandwidth appears constant over a defined range with reduced closed loop gain.
Now, for so-called 'proper' voltage feedback, the feedback network is deliberately arranged so that its loading effect on the summing node is near nil. Viz. varying component values in the feedback network DOES NOT vary LOCAL first stage gain.
See:
http://www.diyaudio.com/forums/showthread.php?postid=954778#post954778
This transistor, therefore, is a differential amplifier, and effectively amplifies the difference between its base and emitter voltages.
Essentially, the resulting error voltage is multiplied by the transistor's transconductance, giving an incremental output voltage that is a function of the magnitude of this transistor's collector load.
No transimpedance involved.
Moreover, with so-called 'current feedback', the feedback network's component values are deliberately chosen so that they constitute a significant load on the first stage.
This means that local first stage gain varies as you vary your feedback resistors......(Remember local gain of simple common emitter stage~Rc/Re???)
Therefore, for low closed loop gains, the Thevenin resistance at the feedback summing node must necessarily increase, since the reduction in closed loop gain is facilitated by increasing the value of the grounded resistor in the feedback network.
Consequently local first stage gain is reduced, which must perforce be accompanied by a reduction in foward path gain.
This then is the mechanism by which bandwidth appears constant over a defined range with reduced closed loop gain.
Now, for so-called 'proper' voltage feedback, the feedback network is deliberately arranged so that its loading effect on the summing node is near nil. Viz. varying component values in the feedback network DOES NOT vary LOCAL first stage gain.
See:
http://www.diyaudio.com/forums/showthread.php?postid=954778#post954778
Mike, finally! a post from you that seems to make sense 😀 ....
This is an interesting way to look at the constant-bandwidth-issue.
In my open loop experiments, where I set the input current level with a resistor from the inverting input to ground, and then I set the gain by the ratio of the Tz load resistor to this other resistor, the absolute value of the resistors also sets the bandwidth. That seems to jive with your explanation.
Hmm. Food for thought.
Jan Didden
This is an interesting way to look at the constant-bandwidth-issue.
In my open loop experiments, where I set the input current level with a resistor from the inverting input to ground, and then I set the gain by the ratio of the Tz load resistor to this other resistor, the absolute value of the resistors also sets the bandwidth. That seems to jive with your explanation.
Hmm. Food for thought.
Jan Didden
cfb illustrative schematic
The attached pdf schematic is a simplified illustration which should make clear the operation of a cfb op-amp. The +_inp, or non-inverting input, is the input of the unity-gain buffer formed by Q1-Q2-Q3-Q4, an npn-pnp Darlington emitter follower. The output of this buffer is the junction of the Q3-Q4 emitters. This buffer output node serves as the inverting input, -_inp.
This node is NOT DRIVEN by the output feedback. Vn, the -_inp voltage wrt ground, must equal Vp, the input voltage at the non-inverting terminal. The grounded resistor R1 carries a current I1, equal to Vn/R1 = Vp/R1. Even if the feedback loop is broken, the input terminals are at the same potential due to the unity gain buffer. The feedback loop DOES NOT drive Vn to equal Vp, the buffer does.
The current in feedback resistor R2, called I2, equals (Vout - Vn)/R2. Under steady state conditions I1 = I2, and In = 0, so that no current enters or exits the neg input terminal.
For example, if Vp = 1.0 volts, R1 = 1.0kohm = R2, then the closed loop gain is 2, so that Vout should equal 2.0 volts. In that case, I1 = 1.0 mA = I2, and In = 0.
But the input, Vp, and output start out at 0V, and the input changes from 0 to 1.0V. The buffer responds immediately, forcing Vn to equal Vp, which is 1.0V. The output is at 0V, so that I1 = 1.0 mA, and I2 = -1.0 mA, or 1.0 mA to the right, from the -_inp towards the output. Therefore In is 2.0 mA exiting the neg input. Q3's emitter sources this 2.0 mA. This current is MIRRIRED over to capacitor C1 via the Wilson current mirror CM3A-CM3B. C1 charges and the voltage across C1, Vc1 increases. This voltage is unity gain buffered by Q5-Q6-Q7-Q8, and Vout = Vc1. Vout is slewing upward, and I2 DECREASES as a result. When Vout = 1.9V, 0.1V shy os the final value of 2.0V, I2 = (1.9 - 1.0)/1.0 = 0.9 mA.
Since I1 is still 1.0 mA, the difference between I2 and I1 is now 0.1 mA, the In is now 0.1 mA, still sourced by Q3's emitter. The mirrored current charging C1 is now 0.1 mA, so Vc1 still slews upward, but a a much slower rate.
When Vout = 2.0V, the final value, I2 = (2.0 - 1.0)/1.0 = 1.0 mA, the same as I1. Therefore In = 0. The mirrored value of this In current is also 0, and the cap C1 current, Ic1 = 0. The voltage on C1, Vc1 remains at 2.0V, as does the output Vout.
To summarize, Vp = Vn always. The feedback loop does not control the input voltages. The feedback loop drives the output in the direction needed to force I2 to equal I1, and reduce In to zero. The cfb servo loop forces the difference CURRENT, I2 - I1 = In, to equal zero. In, the current entering or leaving the neg input, is the error signal.
For those who still insist that the op amp output is driving the emitter, a simple empirical observation will affirm what I've just stated. Connect a switch in series with R2. Opening the switch will result in Vout hitting the positive rail. If you measure Vn, it will equal Vp, or 1.0V. The feedback loop is open and nonfunctional, yet Vn = Vp, due to the input buffer. A vfb is opposite. With the loop open, and 1.0V at Vp, Vn = 0 since Vout is disconnected from Vn, and cannot drive Vn towards Vp. With the vfb, In is always zero, loop open or closed. With the cfb, In must equal I1, since I2 = 0. The results could not be more clear. A simulator will affirm the above.
Case closed.
The attached pdf schematic is a simplified illustration which should make clear the operation of a cfb op-amp. The +_inp, or non-inverting input, is the input of the unity-gain buffer formed by Q1-Q2-Q3-Q4, an npn-pnp Darlington emitter follower. The output of this buffer is the junction of the Q3-Q4 emitters. This buffer output node serves as the inverting input, -_inp.
This node is NOT DRIVEN by the output feedback. Vn, the -_inp voltage wrt ground, must equal Vp, the input voltage at the non-inverting terminal. The grounded resistor R1 carries a current I1, equal to Vn/R1 = Vp/R1. Even if the feedback loop is broken, the input terminals are at the same potential due to the unity gain buffer. The feedback loop DOES NOT drive Vn to equal Vp, the buffer does.
The current in feedback resistor R2, called I2, equals (Vout - Vn)/R2. Under steady state conditions I1 = I2, and In = 0, so that no current enters or exits the neg input terminal.
For example, if Vp = 1.0 volts, R1 = 1.0kohm = R2, then the closed loop gain is 2, so that Vout should equal 2.0 volts. In that case, I1 = 1.0 mA = I2, and In = 0.
But the input, Vp, and output start out at 0V, and the input changes from 0 to 1.0V. The buffer responds immediately, forcing Vn to equal Vp, which is 1.0V. The output is at 0V, so that I1 = 1.0 mA, and I2 = -1.0 mA, or 1.0 mA to the right, from the -_inp towards the output. Therefore In is 2.0 mA exiting the neg input. Q3's emitter sources this 2.0 mA. This current is MIRRIRED over to capacitor C1 via the Wilson current mirror CM3A-CM3B. C1 charges and the voltage across C1, Vc1 increases. This voltage is unity gain buffered by Q5-Q6-Q7-Q8, and Vout = Vc1. Vout is slewing upward, and I2 DECREASES as a result. When Vout = 1.9V, 0.1V shy os the final value of 2.0V, I2 = (1.9 - 1.0)/1.0 = 0.9 mA.
Since I1 is still 1.0 mA, the difference between I2 and I1 is now 0.1 mA, the In is now 0.1 mA, still sourced by Q3's emitter. The mirrored current charging C1 is now 0.1 mA, so Vc1 still slews upward, but a a much slower rate.
When Vout = 2.0V, the final value, I2 = (2.0 - 1.0)/1.0 = 1.0 mA, the same as I1. Therefore In = 0. The mirrored value of this In current is also 0, and the cap C1 current, Ic1 = 0. The voltage on C1, Vc1 remains at 2.0V, as does the output Vout.
To summarize, Vp = Vn always. The feedback loop does not control the input voltages. The feedback loop drives the output in the direction needed to force I2 to equal I1, and reduce In to zero. The cfb servo loop forces the difference CURRENT, I2 - I1 = In, to equal zero. In, the current entering or leaving the neg input, is the error signal.
For those who still insist that the op amp output is driving the emitter, a simple empirical observation will affirm what I've just stated. Connect a switch in series with R2. Opening the switch will result in Vout hitting the positive rail. If you measure Vn, it will equal Vp, or 1.0V. The feedback loop is open and nonfunctional, yet Vn = Vp, due to the input buffer. A vfb is opposite. With the loop open, and 1.0V at Vp, Vn = 0 since Vout is disconnected from Vn, and cannot drive Vn towards Vp. With the vfb, In is always zero, loop open or closed. With the cfb, In must equal I1, since I2 = 0. The results could not be more clear. A simulator will affirm the above.
Case closed.
Re: cfb illustrative schematic
Wrong!
Self-evidently, If the Vn voltage were equal to the Vp voltage, you would have ZERO output voltage.
Claude Abraham said:
Wrong!
Self-evidently, If the Vn voltage were equal to the Vp voltage, you would have ZERO output voltage.
Re: cfb illustrative schematic
This is equally misleading. The feedback network applies a voltage to the emitter of the input transistor. That this (common-emitter) transistor's base is buffered by an emitter follower is purely incidental, as the buffer is outside the feedback loop.
Claude Abraham said:
This is equally misleading. The feedback network applies a voltage to the emitter of the input transistor. That this (common-emitter) transistor's base is buffered by an emitter follower is purely incidental, as the buffer is outside the feedback loop.
Re: cfb illustrative schematic
Equally incorrect; the buffer is outside the feedback loop; it, therefore, cannot 'force' anything.
Claude Abraham said:
Equally incorrect; the buffer is outside the feedback loop; it, therefore, cannot 'force' anything.
Re: Re: cfb illustrative schematic
Agree. That is the classical trap by thinking in VFB terms. There, the (ideally infinite) open loop gain causes the differential input voltage to be very, very small. For an ol gain of 10e5, and 10V Vout, Vin (differential) is just 100uV. We are used to say: "that's zero for practical purposes". Not so in a CCII+!. You NEED an differential input voltage to get an output current and thus voltage, and depending on the current levels, that is quite a bit higher than in a high-gain VFB opamp.
Jan Didden
mikeks said:
Agree. That is the classical trap by thinking in VFB terms. There, the (ideally infinite) open loop gain causes the differential input voltage to be very, very small. For an ol gain of 10e5, and 10V Vout, Vin (differential) is just 100uV. We are used to say: "that's zero for practical purposes". Not so in a CCII+!. You NEED an differential input voltage to get an output current and thus voltage, and depending on the current levels, that is quite a bit higher than in a high-gain VFB opamp.
Jan Didden
http://www.linear.com/pc/downloadDo...NjEJuyhxgd63Y6d9jvJyvhVv4r2EUlDtiMcO0w2EvIu07!-2029508625?navId=H0,C1,C1154,C1009,C1022,P1106,D2342
"The circuit topology is a voltage feedback amplifier
with matched high impedance inputs and the slewing
performance of a current feedback amplifier."
Is the LT1364 like the LM6171 chip ? CFB
"The circuit topology is a voltage feedback amplifier
with matched high impedance inputs and the slewing
performance of a current feedback amplifier."
Is the LT1364 like the LM6171 chip ? CFB
ash_dac said:
mikeks said:
Both Aylward and LT (in the LT1354) use the same trick as National does in the 6171, buffering the negative input of a CFB amp.
Jan, if you use the theoretical model in either the TI or Intesil app notes that has been linked to, there is no voltage difference between the inputs, but they do not assume a current conveyor as a means of implementation. Of course no physical implementation can behave perfectly like that though.
Christer said:
This, then, should confirm, to even the most benighted, obstinate and obdurate, that their theoretical model is not worth the paper it's printed on.
mikeks said:
This, then, should confirm, to even the most obstinate and obdurate, that their theoretical model is not worth the paper it's printed on.
Of course it is, as I have explained before.
Otherwise you will have to reject the usual op amp model too, since it is impossible to implement, and I assume you never use Ohms law, since it only works for perfect resistors.
You can of course refine the theoretical CFB model to better approximate real implementations. It is so trivial to do so I leave it as an exercise for you. I do think they show how to do it in one of the app notes, though, should you get stuck. 😉
mikeks said:
Mike, I guess it is not illegal to use somebody else's sig to make a point, however misguided, in your own posts, but I really wish you would stop that. It gives the implication that whoever is the originator of the sig agrees with you unconditionally, which is not true by a long shot.
Surely you have the required intelligence and creativity to come up with a forcefull statement all by yourself?
Jan Didden
Hi Jan,
I was under the impression that this quote is due to one Jamie Whyte, and as such, provided due credit is given to its author, anyone is free to cite any part of this work.
Cheers.🙂
I was under the impression that this quote is due to one Jamie Whyte, and as such, provided due credit is given to its author, anyone is free to cite any part of this work.
Cheers.🙂
mikeks said:
As I said, it's probably not illegal what you do. Still, I'd like you NOT to cut-and-past use my sig. How about common decency, that ring a bell with you?
Jan Didden
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