Cronus - It's about time.

[schultzsch]

I gave it again a try and now I can hear the track that is streaming but there is something like a pink noise present there that remains for the entire streaming period.

How could the vcxos be damaged if on the scope they give a good trace ?

 

[Blitz]

Incidentally, the clocks on the Rhea modules are Crystek CCHD-957s. The boards allow you to mount just about any clock though.

So, it will accept as well the oven controlled crystal oscillators like Pulsar ?

Regards

 

[Russ White]

So, it will accept as well the oven controlled crystal oscillators like Pulsar ?

Regards

As long as it is the same type of output signal [CMOS]

 

[Russ White]

I gave it again a try and now I can hear the track that is streaming but there is something like a pink noise present there that remains for the entire streaming period.

Have you disabled SPDIF autodetect? (Sw 2:6)

 

[schultzsch]

Yes, I did it now. but still the same.

It`s this a must that spdif autodetect must be off when running sync?

 

[Russ White]

It`s this a must that spdif autodetect must be off when running sync?

Any time you know you will be running just PCM or DSD you should always disable SPDIF auto detect - because at high sample rates the detection circuit can false positive and cause unlocks.

Also just to be clear when I try to help - I will expect you are specifically trying my firmware (not your own) for these tests (because I am only certain what I wrote). And also you should ensure (at least for the tests) that the cronus is powered up *BEFORE* the DAC - and not at the same time to eliminate the possibility of the controller not correctly initializing the DAC because it has no master clock. A controller can't control the DAC with no master clock present and the Cronus startup can be slightly slower than the DAC's. This is why Async is much simpler.

 

[Blitz]

Is Hcmos compatible ?

http://www.pulsarclock.com/ds/Pulsar_Clock.pdf

...need to ask as I dont know if there are different cmos-versions and how they relate to each other...

 

[schultzsch]

You are right about startup times, Cronus indeed starts up after the dac if they are powered together the same time.
In the beggining I was hearing a loud pop up sound when changing from pcm to dsd or when skipping through a dsd file.
After starting up b3 after cronus solved this problem and since then I never powered them the same time.

 

[schultzsch]

For curiosity I disoldered C10 from Cronus board. This shortens a lot startup time for Cronus and now if I start b3 and cronus together I have no more that pop up sound resulting from the synchronization problem.

This is not for free, C10 is on the bypass pin of adm7150 and removing him you will end with a little more noise on regulators output.

 

[Russ White]

You are right about startup times, Cronus indeed starts up after the dac if they are powered together the same time.
In the beggining I was hearing a loud pop up sound when changing from pcm to dsd or when skipping through a dsd file.
After starting up b3 after cronus solved this problem and since then I never powered them the same time.

This happens because the channel remapping registers are at their default state. Which will introduce DC (the nasty pop you are hearing). This is a definite indication that the controller is not touching important registers. This is natural because you cannot set registers on the DAC when there is no master clock.

 

[Russ White]

For curiosity I disoldered C10 from Cronus board. This shortens a lot startup time for Cronus and now if I start b3 and cronus together I have no more that pop up sound resulting from the synchronization problem.

This is not for free, C10 is on the bypass pin of adm7150 and removing him you will end with a little more noise on regulators output.

Sure you could do that - but I would not recommend it.

I am working on a new firmware version for B3SE that will make it much easier to work with late arriving or even disappearing clock signal. I have been working on it over the weekend and am glad to report it is working quite well. It should eliminate the clock power up sequence sensitivity.

Using the new firmware I can now add and remove the MCK at will without upsetting the state of the DAC/Firmware. There are some other benefits as well.

I will post more details shortly.

 

[schultzsch]

Learned another useful thing.
Cronus has to start first after him dac and iv and the last that starts has to be the controller se he can send correctly the register settings.
Now my question is how important it is if the iv starts after the dac?

If dac starts first and iv after will de dac go in current mode?

 

[Russ White]

It depends on the type of I/V stage, but for my I/V stages it does not matter at all - I put my analog(I/V) PS on the same switch as the DAC.

The DAC never switches into "current" mode - it only has one mode. Current vs voltage is purely a view on the impedance of the next stage.

 

[schultzsch]

Thanks Russ.

I am planning to build an lt3081/3091 power supply to power up iv and a 4 x lt3081 to power up the dac, controller and cronus.
These boards will be used as preregulators.
I also want to use some crc filtering between transformer and lt's which will produce some startup delay also.
Delays here will be different because each board that I want to power up consumes different currents and to get the preregs at the same output voltage I have to use different resistors in the filters for each preregulator
I never saw in a commercial products crc filters on digital power lines, only on analog side.
And this makes me curious again, very curious I can say
Nobody uses crc filters on digital ps's because of the startup delay that these filters create or for something else like final product cost and efficiency ?

 

[Russ White]

I just released the new beta B3SE firmware (still beta until 1.0.0) on github

https://github.com/russwyte/Buffalo-3SE-on-board-firmware

This firmware is very well suited to sync clock builds - because it does not depend on the DAC always being accessible and will correctly reset whenever the DAC does (because of clock loss etc)

If you want to beta-test the firmware - use an AVR Dragon or equivalent programmer with HVSP to program your ATTiny85 with the hex from latest release link.

I have tested this firmware in a sync setup where the master clock was significantly delayed and it worked like a charm. Also I can remove the master clock and put it back and the DAC recovers nicely.

Feedback and pull requests welcome.

Cheers!
Russ

 

[schultzsch]

Looks like a good homework for tonight

 

[schultzsch]

Any info for the default switch positions?

 

[Russ White]

There is no change from the current firmware, but I will add a switch map to the readme.

 

[schultzsch]

Never tought that is so hard to program this little chip. I spent the last two hours reading on internet but still nothing, no code uploaded.
Since I had never done it before I do not know from where to start.

I have at hand an usb-ttl ftdi cable which I can use to program attiny85.

Now the problem is how to upload the main.c file to arduino ide. The program recognizes only .ino or .pde files

What you guys use to upload .c files to attiny ?


Can somebody give me a link with a tutotial or something, I would really apreciate it.

Thanks

 

[Russ White]

I believe you will need a HVSP type programmer like the AVR Dragon. I believe ISP won't work because the Reset Pin has to be disabled.(I will try to to confirm this later)

You can use AVRDude or Atmel Studio to program the device.

All you need is the *.hex file from the release and the Fuse bits from the readme.

https://github.com/russwyte/Buffalo-3SE-on-board-firmware/releases/latest