CFP oscillation woes

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AndrewT said:
Just logged on and this caught my eye, not read the other responses yet.
8mA and 560r =4.48V across the gate/source of a Lateral FET.
This is bonkers.

If the sim is predicting 4.48Vgs then go and look at the datasheet graphs and you will see it is telling you lies. Either you have set up the sim wrongly or the LFET model is actually a vFET.
Measure the circuit gate/source voltage and measure the 560r volts drop.

Sorry, I forgot to post this at the time. As the are at the moment:

906D (M1) GS = .63V

901D (M2) GS = .27V

I'll check what I have setup in the sim. The FET mdoels came from the manufacturer as subcircuits, but I may have set something else up incorrectly. I'm still fairly new to the simulator in general, and it's been a steep learning curve.
 
ian_elvar said:
I take it you mean R3 to 1K? Yes, the CL gain is a little unconventionally high at the moment. It will be a little noisier with higher value resistors, but in this case I think that's an acceptable trade for stability. How does it help though?
The increase of noise is insignificant. The higher resistance provides more HF phase margin, provides a more standard loading for the source, and allows you to use a smaller and better quality C7 in due course.

Ok, so you're suggesting cutting down a bit more of the feedback. We're getting away from the value that AKSA and Elvee and suggested from his simulation though, so I'll try to run it myself.
22 ohms was an arbitrary value not customized for your output stage. I've done my own simulation and I don't think 22 is high enough.
If you are concerned about the amount of NFB, we'll be raising that later.

I agree, it makes sense to keep the driver current where it is. Do you not mean R27 1K and R26 2K2 though? The 906D has double the capacitance of the 901D, so surely it makes sense to put the larger cap on the 906D gate? Or am I missing something?
The value of the gate resistor is inversely proportional to the capacitance. You want R x C to be similar.

There will be an output network, but it's off board on the DC protection PCB.
Good.

It's certainly well behaved just wiggling a voltage into the air though.
Famous last words. :clown: 🙂
 
Ian,
I forgot to reiterate what I said in an earlier post. Between C2 and R1 you need to insert a resistor of 1.5k to 2k. This resistor forms the low pass filter with the 1nF cap.

45mV is ok. You may find the offset varies from one SSM part to another, so if you have them socketed you can try another one.

I bet you can't wait to hear it.


optional:

Now things are still working well, and you've lowered the gain of the CFPs, you can reduce the value of C1. 150pF is probably 3 times too high but there are some other things that may need to be done before you can go the whole way. However, I think it safe to reduce it to 100pF right now if you have a cap handy. Best to use a quality cap like polystyrene, polypropylene. Avoid ceramic or mica.

Note that the 33 ohms in the CFB reduced their feedback by about 3dB. Using 33k/1k rather than 10k/220 has increased the global feedback by 2.6dB and changing C1 to 100pF will increase the feedback (above a few kHz) by 3.5dB.

Brian
 
Brian

It's OK, I actually did put in the resistor but neglected to mention it in my post.

I can't remember if I mentioned before, but it's actually BC556/547s in the input at the moment. They're turned pin sockets in the baord, so I just chopped the transistor leads and pushed them in. SSM's are expensive, so I started with something cheaper in case I make any mistakes in that area.

Changing the resistors had a fair effect on the DC offset, so I might try matching them. Offset should be better with the SSM's anyway - that's part of the reason I thought I'd try them. As you say, 45mV isn't the end of the world, but I'm sure it can be improved.

I know what you're saying about changing C1 - I wasn't intending on having that as the final value, just a starting one - but I think I'll leave it where it is just for the moment to make sure I've got a good margin. It's a silvered mice in there at the moment, which I chose after reading a few threads on the subject in this forum, and I'm afraid that's all I've got around that value apart from ceramic. Why would you advise against mica?

Next stage for me is more testing and catching up on simulation, shortly moving onto a dummy load. You're right, I'm pretty eager to see how it perform, but I'm equally nervous about what will happen when it's connected to a real load!

Thanks for your continued assistance 😎
 
I got brave and decided it was time to put it to the test with a proper speaker, and the 5MHz oscillation returned on the top half of the swing. So I reasoned that the base stopper might be a little low at 1K and swapped it back for the 2K2 which has cured the problem again.

This doesn't entirely suprise me, as this app note that I found a while ago suggested that the should be 1K5 or so and especially in light of Anthony's comments on the lack of internal base stoppers in these dual die devices.

It's possible that the layout isn't helping either, so I'll look into how I can improve it as Eva suggested.

I'm stepping up the testing very slowly now, but for the moment it seems pretty stable.
 
Well, well.
Did you have the series inductor in place with the speaker?
8-ohm nominal speaker, I presume, and at what sort of pos V did the signal fuzz up and what frequency sinewave?

The trouble is your FETs are now unbalanced, and 2.2k is almost too much, as it is, in terms of current drive. Also, the output stage is clearly still marginally stable and I would want to see a more convincing fix.

I'll give this some more thought later when I've got more time to review the datasheet.
Brian
 
Hi Ian,
The forward to those datasheets is somewhat foreboding. With regard to replacing Hitachi devices, in addition to large gate R they also recommend adding a gate-drain cap, 22pF to 47pF. This isn't ideal but it will reduce Cgd variation with Vdg and should allow a reduction in gate R for M2 which helps with current drive.

I recommend trying the following values:
R26 1k, add 22pF cap from D to G of M1

R27 1.5k, add 47pF cap from D to G of M2

Locate the caps as close as you can to the FET pins, short leads.

Try a sinewave into the speaker again and note at what amplitude the oscillation starts to appear, if it does.
It is a good idea to try a resistive load too, say 4 or 5 ohms (have you got some high power resistors in your kit?).
 
Hi Brian

I've been running a lot of spice simulations during the day, very similar to what Elvee was doing before, but with the full symetrical output circuit, and the best transistor/FET models I can get my hands on. The 1381/3503 were easy to get from fairchild, but I had to email semelab for the FET models.

I can see why the bias was causing oscillation, and why the OP was so unstable without those extra resistors now. I'm beginning to wonder whether this is a workable solution at all though, as it's very easy to get the OP to generate wild phase changes that seem to match fairly closely how the circuit behaved in real life.
I might be able to get it stable on the bench, but with it balanced on such a knife edge, can I guarantee it won't do something nasty if it's presented with an odd load or something I hadn't accounted for? I guess this must be at the back of anyone's mind who ever created an amplifier!

It would be nice to have a solution though, as I wouldn't be doing this (or having so much touble) if it was easy in the first place.

I'll give the G-D caps another go. I tried them before after reading that app note, but they made it 10 times worse. Admittedly this was before tha additional resistors were installed, so I'll let you know how it goes.

I'm also looking into the suggestion of putting bipolar followers before the gates, which i'm in the process of simulating.
 
Eva said:
Common practices such as ............... routing the supply rails through the sides of the PCB and placing the small signal circuits in the center are completely wrong.


There is nothing wrong with this as long as the supply rail tracks enclosing the small signal circuitry do not carry the output stage / load current (ie the supply wires connect as close as possible to the output stage).
 
At 5Mhz any oscillation is likely to be local. This frequency is usually well above global feedback bandwidth.

Enclosing the small signal circuits with the supply rail tracks is not that wrong until the decoupling capacitors are placed on the opposite side of the PCB with respect to the output stage and the ground conenction is made at the opposite side too. This is quite common PCB layout practice on linear amplifiers.
 
it seems you might want to (as odd as this suggestion sounds) slow down your input/VAS.

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1028,P1219,D4138

starting at pg 86 is a chapter about causes of oscillation. one of those causes is an input/VAS with blinding speed matched to an output stage that crawls. here's a quote from pg 88:
---------------------------------------------------------------------------
A good way to eliminate loop-caused oscillations is to limit
the gain-bandwidth of the control amplifier. If the booster
stage has higher gain-bandwidth than the control amplifier,
its phase delay is easily accommodated in the loop.
When control amplifier gain-bandwidth dominates, oscillation
is assured. Under these conditions, the control
amplifier hopelessly tries to servo a feedback signal which
consistently arrives too late. The servo action takes the
form of an electronic tail chase with oscillation centered
around the ideal servo point.
Frequency response roll-off of the control amplifier will
almost always cure loop oscillations. In many situations it
is preferable to brute force compensation using large
capacitors in the major feedback loop. As a general rule, it
is wise to stabilize the loop by rolling off control amplifier
gain-bandwidth. The feedback capacitor serves only to
trim step response and should not be relied on to stop
outright oscillation.
-------------------------------------------------------------------------

your "control amplifier" is your input/VAS and your "booster" is your output stage.......
 
Eva said:
At 5Mhz any oscillation is likely to be local. This frequency is usually well above global feedback bandwidth.

Enclosing the small signal circuits with the supply rail tracks is not that wrong until the decoupling capacitors are placed on the opposite side of the PCB with respect to the output stage and the ground conenction is made at the opposite side too. This is quite common PCB layout practice on linear amplifiers.


Well unless the decoupling caps, ground connection and +/- rail connections are in the wrong place, I contend that there is nothing wrong at all with running supply tracks along the top and bottom of the board with the small signal circuitry inbetween.
 
Regarding the PCB layout, what do you mean by the 'main ground'? If you mean the ground connection which the input, feedback and VAS buffer connect to then, it's in the middle of the board with all the components that connect to it packed around it, and has its own return to the star point. Main filtering is done as close the the power rail connections as I could get it, and sits between them and the small signal parts, opposite the power components. Both positive and negative rail decoupling have their own connections back to the star point.
The vertical track on the left of the board only carries some extra rail decoupling, and the grounds for the current sources.
The Zobel also has its own connection back to the star point.

I'm pretty sure 5MHz is well above the bandwidth for this circuit, so I think we can rule out global oscillation. Global gain starts rolling off at about 30KHz anyway.
Thanks for the article though, I'll keep a copy of that.

Pete - It was something I was thinking about, so maybe I'll try it and see what happens, but in simulation it doesn't look all that promising above what we've already achieved with 33r.

As ever, thanks to everyone for their continued input.
 
And I forgot to mention that I'm going to try something that may or may not be slightly unconventional this evening. Simulation suggests that keeping the inductance on the source connection low is the best way to keep gain peaks and phase changes out of the way, so I'm going to try making the power connections straight to the bolts that run through the ali mounting plate to hold the FETs down and make the source connection with the PCB.
I've got a car ignition system and ECU that I'm tweaking on the bench at the moment, but I'll update when I get the amp set up again this evening.
 
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