dadod,
I will try to take a look a bit later.
I think you have to change your compensation (TIS shunt) and the feedback resistor value must be decreased. Just for example, on my nx-amp, the feedback resistor is 540 Ohms (5 off 2,7k in parallel). This will speed your amp up. On the sx-Amp, its 200 Ohms. Both these amps slew above 140 V/us (sx IIRC is >200 V/us)
I will try to take a look a bit later.
I think you have to change your compensation (TIS shunt) and the feedback resistor value must be decreased. Just for example, on my nx-amp, the feedback resistor is 540 Ohms (5 off 2,7k in parallel). This will speed your amp up. On the sx-Amp, its 200 Ohms. Both these amps slew above 140 V/us (sx IIRC is >200 V/us)
I would like if you succeed, but neither of your amp is using current conveyour and here is different play.
Yes, this is true. But, maybe the solution is to think simple here, which is one of the things CFA can do well 😉
Have you looked at the drop across the series resistor between the current output and the pre-drivers (R42)?
Thanks
-Antonio
Dadod, I took a look last night. I am not able to easily get the SR up without some drastic modifications. Although there has been some discission here about Current Conveyors (CC), I dontr think we have sorted out exactly how to apply this technique successfully yet -non linear loadibng effects being the biggest concern.
The quicest way to up the SR is to reduce the feedback resistors which I have done, and the comp cap (total series value).
If I mod your TIS stage to beta enhanced conventional design and make the outpput a standard triple, I can get to ~200V/us and 5-15ppm at 20 kHz. However, this is just my quick look, and there is quite some more work to be done to improve PM and stability. Note these figures are with TPC. I think to move this design forward, you will need to go back to your CC FE and perfect that, and then move onto the output stage.
However, I am more and more thinking that CC may not be ideal for a discrete CFA, since with very simple, standard building blocks you should be able to get to sub 10ppm at 20 kHz.
The quicest way to up the SR is to reduce the feedback resistors which I have done, and the comp cap (total series value).
If I mod your TIS stage to beta enhanced conventional design and make the outpput a standard triple, I can get to ~200V/us and 5-15ppm at 20 kHz. However, this is just my quick look, and there is quite some more work to be done to improve PM and stability. Note these figures are with TPC. I think to move this design forward, you will need to go back to your CC FE and perfect that, and then move onto the output stage.
However, I am more and more thinking that CC may not be ideal for a discrete CFA, since with very simple, standard building blocks you should be able to get to sub 10ppm at 20 kHz.
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Gentlemen, I'm having trouble understanding how the Boxall/Baxandall pair reduces distortion .. particularly the bit about re-cycling the base current.
Does anyone have a link to sumfink unerstanerbal 2 wun hu didden wen to skul en dunno to reed en rite?
I can see the use of complementary devices (at similar currents) leads to a lot of Vbe THD cancellation and how by feeding the main VAS Q from Lo Z, it reduces the evil effect of modulated Ccb.
__________________________
I think Q1/3 is Boxall where Q3's base current is 'returned' to its emitter. Q2/4 dun do this and may be considered simply an EF feeding the VAS like Blameless. Both are enhancements to the simple PNP VAS Q5.
Comments from yus gurus please.
Does anyone have a link to sumfink unerstanerbal 2 wun hu didden wen to skul en dunno to reed en rite?
I can see the use of complementary devices (at similar currents) leads to a lot of Vbe THD cancellation and how by feeding the main VAS Q from Lo Z, it reduces the evil effect of modulated Ccb.
__________________________
I think Q1/3 is Boxall where Q3's base current is 'returned' to its emitter. Q2/4 dun do this and may be considered simply an EF feeding the VAS like Blameless. Both are enhancements to the simple PNP VAS Q5.
Comments from yus gurus please.
Attachments
Thanks Bonsai, you are probably right about CC use in CFA power amps, but I am intriqued how to use CC in the best way. I will try to solve SR problem, but first I need to finish my other project(GainWire pre amp).
BR Damir
Thanks Antonio,
You are right, it's better without that resistor but not much(if it's value is higher bad influence is higher too, 1k does not change much). It was leftover from my pre amp project.
BR Damir
I read the famous Hawksford paper on "Enhanced cascode" repeatedly before I started to see his point about how base current is recycled.
It is easy to find on the web if you don't already have it.
Best wishes
David
Hi Dadod.
Look at the transient plot attached.
First stage is fast enough. (Node 35 is Q8 collector in the VAS stage). But the arrangement Q31, Q32 and C1 is the parts that limits the slewrate.
Q31 and Q32 is conducting through C1.
You need to find another way to design your auto bias system.
I agree totally with Bonsai
BR Sonny
I am attaching the qx-Amp schema.
This takes a very different (less complex) approach to dadods amp, and uses a conventional CFA structure although TPC is not usually applied to CFA's
Note this is for a big (>300W) amp, so this is why there are many output devices - which also helps with distortion.
SR ~120V/us (can be improved with more work)
ULGF ~3MHz
Closed loop -3dB >800kHz
Ddistortion at 20 kHz 312W out standard 7ppm
as above, but with AFEC engaged 2ppm
Below 200W distortion sub 1ppm
Importantly, distortion spectra mostly 2nd and 3rd
Compensation: TPC
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 7.163e+01 1.000e+00 -1.61° 0.00°
2 4.000e+04 1.481e-04 2.067e-06 -25.92° -24.31°
3 6.000e+04 4.928e-05 6.880e-07 146.54° 148.16°
4 8.000e+04 1.868e-06 2.608e-08 35.24° 36.85°
5 1.000e+05 1.263e-05 1.763e-07 -41.96° -40.35°
6 1.200e+05 4.947e-07 6.907e-09 -55.30° -53.69°
7 1.400e+05 1.296e-05 1.810e-07 -152.96° -151.35°
8 1.600e+05 4.718e-07 6.587e-09 -6.60° -4.99°
9 1.800e+05 1.026e-05 1.433e-07 -108.61° -107.00°
Total Harmonic Distortion: 0.000220%
.step rafec=1e+012
N-Period=1
Fourier components of V(vo)
DC component:-0.665815
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 7.136e+01 1.000e+00 -1.62° 0.00°
2 4.000e+04 1.737e-04 2.434e-06 -59.18° -57.55°
3 6.000e+04 4.592e-04 6.435e-06 74.98° 76.61°
4 8.000e+04 8.320e-06 1.166e-07 -81.34° -79.72°
5 1.000e+05 6.989e-05 9.794e-07 -125.12° -123.50°
6 1.200e+05 2.951e-06 4.135e-08 -6.20° -4.58°
7 1.400e+05 5.375e-05 7.532e-07 130.95° 132.57°
8 1.600e+05 1.081e-06 1.515e-08 96.64° 98.26°
9 1.800e+05 3.448e-05 4.832e-07 176.05° 177.67°
Total Harmonic Distortion: 0.000701%
Note, in my view, anything below about 30ppm is very good, as long as it is low order.
Loop Gain at 20 kHz = 60dB
With AFEC, the PSRR issues normally associated with CFA (so PSRR typically no better than 50 or 60dB at 1 kHz) are removed - the PSRR is equal or better than VFA at 90 dB+ and it holds well up to HF, and you get DC servoing as well. The other way to get this peformance is with cap mulipliers, but even then, you cannot quite match the performance of AFEC for PSRR.
I will probably start layout on this towards the end of the year after doing a bit more design work.
This takes a very different (less complex) approach to dadods amp, and uses a conventional CFA structure although TPC is not usually applied to CFA's
Note this is for a big (>300W) amp, so this is why there are many output devices - which also helps with distortion.
SR ~120V/us (can be improved with more work)
ULGF ~3MHz
Closed loop -3dB >800kHz
Ddistortion at 20 kHz 312W out standard 7ppm
as above, but with AFEC engaged 2ppm
Below 200W distortion sub 1ppm
Importantly, distortion spectra mostly 2nd and 3rd
Compensation: TPC
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 7.163e+01 1.000e+00 -1.61° 0.00°
2 4.000e+04 1.481e-04 2.067e-06 -25.92° -24.31°
3 6.000e+04 4.928e-05 6.880e-07 146.54° 148.16°
4 8.000e+04 1.868e-06 2.608e-08 35.24° 36.85°
5 1.000e+05 1.263e-05 1.763e-07 -41.96° -40.35°
6 1.200e+05 4.947e-07 6.907e-09 -55.30° -53.69°
7 1.400e+05 1.296e-05 1.810e-07 -152.96° -151.35°
8 1.600e+05 4.718e-07 6.587e-09 -6.60° -4.99°
9 1.800e+05 1.026e-05 1.433e-07 -108.61° -107.00°
Total Harmonic Distortion: 0.000220%
.step rafec=1e+012
N-Period=1
Fourier components of V(vo)
DC component:-0.665815
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 2.000e+04 7.136e+01 1.000e+00 -1.62° 0.00°
2 4.000e+04 1.737e-04 2.434e-06 -59.18° -57.55°
3 6.000e+04 4.592e-04 6.435e-06 74.98° 76.61°
4 8.000e+04 8.320e-06 1.166e-07 -81.34° -79.72°
5 1.000e+05 6.989e-05 9.794e-07 -125.12° -123.50°
6 1.200e+05 2.951e-06 4.135e-08 -6.20° -4.58°
7 1.400e+05 5.375e-05 7.532e-07 130.95° 132.57°
8 1.600e+05 1.081e-06 1.515e-08 96.64° 98.26°
9 1.800e+05 3.448e-05 4.832e-07 176.05° 177.67°
Total Harmonic Distortion: 0.000701%
Note, in my view, anything below about 30ppm is very good, as long as it is low order.
Loop Gain at 20 kHz = 60dB
With AFEC, the PSRR issues normally associated with CFA (so PSRR typically no better than 50 or 60dB at 1 kHz) are removed - the PSRR is equal or better than VFA at 90 dB+ and it holds well up to HF, and you get DC servoing as well. The other way to get this peformance is with cap mulipliers, but even then, you cannot quite match the performance of AFEC for PSRR.
I will probably start layout on this towards the end of the year after doing a bit more design work.
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Thanks Sonny,
I suspected that the main problem was in OPS, and simulated input gain stage in isolation, SR is 120V/usec not much but good enough. Q32 and Q32 are part of error correction and it looks that this has to be compensated differently.
BR Damir
Very good Bonsai,
I can see from your CFA schematics that you use diamond input exclusively, try Boxall/Baxandall instead and you can get even lower distortion. Otheradvantage is simpler DC offset seting by changing one CCS current a bit.
BR Damir
wild card
Throwing in a wild card. The various mirror topologies can also be configured to operate in class AB, which allows good-sized resistive ballasting for lower input-referred noise, but reduces the required voltage headroom for pulsed currents.
I haven't been able to locate the EDN article Marsh referenced (EDN's search engine sucks, and maybe they just don't maintain online archives past a few recent issues) but I'm going to do a noise inventory on a CFA design for pedagogical purposes, showing the contribution of internal sources, rather than just what total noise is based on tabulated series and parallel input noise.
Throwing in a wild card. The various mirror topologies can also be configured to operate in class AB, which allows good-sized resistive ballasting for lower input-referred noise, but reduces the required voltage headroom for pulsed currents.
I haven't been able to locate the EDN article Marsh referenced (EDN's search engine sucks, and maybe they just don't maintain online archives past a few recent issues) but I'm going to do a noise inventory on a CFA design for pedagogical purposes, showing the contribution of internal sources, rather than just what total noise is based on tabulated series and parallel input noise.
Hi Richard,
See: "Reduction of transistor slope distortion in large signal amplifiers" in Malcolm Hawksford - Publications
and: Cascading C4S in a PSU
Cheers, E.
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Thanks dadod
I try to keep it simple - dont chase only distortion numbers. 😉
For DC offset, AFEC will take care of this, but you can also just use a pot across the the front end zener supply, plus series resistor anf noise filter cap (see nx-Amp for example). If you lay the diamond out so all the transistors are close together (easy!) the DC performance is remarkably good.
I would like to see the CC work - my interest here is that we should be able to then independently define the loop gain from the CLG. But, we should try to keep it simple.
I try to keep it simple - dont chase only distortion numbers. 😉
For DC offset, AFEC will take care of this, but you can also just use a pot across the the front end zener supply, plus series resistor anf noise filter cap (see nx-Amp for example). If you lay the diamond out so all the transistors are close together (easy!) the DC performance is remarkably good.
I would like to see the CC work - my interest here is that we should be able to then independently define the loop gain from the CLG. But, we should try to keep it simple.