These are not my measurements.
I agree in my comments that 1V RMS is way too high. I also suspect that the implementation used Sowther's own recommendation to load only the secondary, which maximises distortion.
400mV P-P is 141mV RMS.
This means that to get 2V output (the normal level) 23dB additional gain is needed.
As a result those transformer cannot be used as sole analogue stage in a DAC intended for use in most systems. Hence, if you recommend such transformers, you need to state the limitations.
If the transformer were limited to 0.1V out and fed from a 7.5 Ohm current to voltage conversion resistor on the primary, the results would be rather different. How many could use this in their system like this is another story.
FWIW, in my particular case the DAC needs a maximum output of +20dBu (7.75V) @ 0dBFS. Before deciding on bipolar transistors as main part of the Analog Stage the "first cut" intended to use classic pro audio transformers and a 5687WB as differential stage with cathode feedback through the transformer (transformers Reichenbach Engineering / Peerless with high nickel cores).
By the time the transformers, power supplies etc. were added the BOM just for that part started pushing 2K USD, so I decided to retrench. The cost for a mostly open loop Transistor based circuit is nominal.
Thor
ThorstenL, you have completely failed to consider that I don't need 2v RMS out. I am not making a commercial product.
My NAD 326BEE premap inputs are 160mv into 100k so no additional gain is needed. I don't use any other secondary load resistor as I found no sonic benefit when using 6.8-10k. The preamp output drives a DSP/Crossover and volume control is about 30% from minimum.
My NAD 326BEE premap inputs are 160mv into 100k so no additional gain is needed. I don't use any other secondary load resistor as I found no sonic benefit when using 6.8-10k. The preamp output drives a DSP/Crossover and volume control is about 30% from minimum.
74HCT04 has big Tpd and jitter rise significantly in comparison with simple fast flip-flop 74LVC1G74. Is not better to use multiple flip-flops in series for the clock divider? 🤔
no i dint mean that... i sait that most of the usb/i2s modules using 22.579 / 24.576 MHz MCK oscilators. And they are rated up to 352.8 KHz / 384 KHz
In i2s stadard we have 2 x 32 = 64 bit word for 1 SR cycle that is WS or LE signal
So for 1xFS it contains 64 BCK
When SR goes to 352.8 KHz / 384 KHz (that is WS or LE i2s line) we have still 64 bits
so
BCK = 352.8 KHz x 64 = 22.579 MHz (for 44.1KHz SR base) or
BCK = 384 KHz x 64 = 24.576 MHz (for 48KHz SR base)
These are exact F as MCKs Fo, so MCK = BCK
I measure this with the scope...
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Recklocking is not posibile if we have same Fo at data and clk inputs on FF.
CLK (MCK input) must be minimum 2 x higher than DATA (BCK, DATA, WS I2S lines). Or 2N higher and same rising edge as data rising edge.
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So with interfaces with 22.579 / 24.576 MHz MCK oscilators on PC bpard recklocking is posibile only up to 176.4 / 192 KHz SR because MCK then 2 x higher than BCK line we can recklock tis digital line with succes. Other lines are less Fo and they are not an issue...
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Google for Metastability
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BTW
JL sound has double Fo MCK oscilators on board 45.158 MHz / 49.152 MHz ( @ Pin 18 ), so recklocking of BCK from max SR is possible. And these option has to be used for CLK input of FF for reckoking...
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Interesting. The BCK is twice the official DS spec... Hmmm. Seems we have the same 'scope...
I agree that shifting the LE pulse would be good. Not sure making it wider will help if this triggers reliably. I would shift it all the way to before the first bit clock. It also suggests that the decoupling if we use SIM mode with timing similar to JL Audio we need to watch reclocking speeds and decouple the TDA1541 for 22.XX/24.XX and up ripple on +5V. That is a tough order. And of course it is way past official maximum speed for the pins, way I read the various datasheets.
Hmmmm.
Maybe just me, BUT all else being equal I would tend towards always using the lowest possible frequencies for all clocks, like so:
| Sample Rate (IIS WCK) | IIS MCK | IIS BCK | 1541 SIM BCK | 1541 SIM LE | DEM |
| 44.1 | 22.5792M | 2.8224M | 0.7056M | 44.1 | 176.4 |
| 48 | 24.5760M | 3.0720M | 0.7680M | 48 | 192 |
| 88.2 | 22.5792M | 5.6448M | 1.4110M | 88.2 | 352.8 |
| 96 | 24.5760M | 6.1440M | 1.5360M | 96 | 384 |
| 176.4 | 22.5792M | 11.2896M | 2.8224M | 176.4 | 705.6 |
| 192 | 24.5760M | 12.2880M | 3.0720M | 192 | 768 |
| 352.8 | 22.5792M | 22.5792M | 5.6448M | 352.8 | 1,411.2 |
| 384 | 24.5760M | 24.5760M | 6.1440M | 384 | 1,536 |
This suggests that the IIS clock should be divided by 4 before clocking out the 16 bit's of data stored in our shift registers (for a hardware solution).
The on-chip coupling is almost entirely capacitive via the substrate and thus the higher the frequency, the more coupling. I think overall this will do a better job lowering actual noise than this idea of "let's maximise noise for a certain time and then turn the noise off and measure the average". Averages only work if the whole system is designed for that.
I suspect that the Chinese CPLD boards cribbed from the source and have the same behaviour. Why is nobody doing independent thinking anymore?
I might have to rethink everything. Do a totally new discrete IIS->SIM converter to my requirements. Quel dommage, this is degenerating into work.
Might as well just use IIS and gate the bit clock to only work when there is data for TDA1541 to use, that would do the same in terms of having "silent time".
Thor
Btw BRmax (maximum input bit rate) from data-sheets indicating 12 Mbits / sec for tda1540, and 6Mbits / sec.
I do consider it. You might have read my comments on these measurements from
But have you considered to tell all those that you promote Sowter 1465 transformers to "use them only with 140mV output, do not expect 2V line out, or even 1V if they expect even competent performance?
All I ever read "bifilar wound Sowter Transformers are the best" without any qualifications or limitations. You might find peeps believe this and think iot works for TDA1541 -> 2V line out directly.
My preamp is a passive 10K P&G 128mm Fader. My own amplifiers are usually designed for 1V input for full power. So to me your best solution is not useful. And from reading what you write I get no such implication.
You mean you use a TDA1541 DAC into a high gain solid state preamplifier and then into an AD Converter, a DSP and then an DA Converter IC and we are debating the sonic purity of a TDA1541 analogue stage?
Thor
PS, more on how that CD Player with those transformers and more measurements:
https://www.bramjacobse.nl/wordpress/?p=6167
He made a subpair pcb, pushing his idea od good transformer, but as i said, whatever floats his boat. If its good for him, he be him 😁
The part I recommend is this:
How you create the input signal - your call.
I know what I will use, but that is the result of needing something that comes in DIP/DIL cases and is fast enough, leaving only a very short shortlist.
All else being equal always use the SLOWEST non-saturating logic available That means mostly not CMOS (AUC/AUP are exceptions) but ECL or Schottky.
Thor
Used the way he does the transformer will work pretty well, no idea of the PCB. TDA1541 is not really that hard.
I have no beef with anyone liking whatever the like and not taking sh!t over from anyone. In fact that's my motto.
But that is not the same like me telling everyone "go out and buy dope and a gun" simply because where I am it happens to be legal (for now), regardless if they like weed, guns or can make use of them in their life...
Or if whenever someone tells people generically something that disagrees with their believes go out of their way to be negative. Tolerance is needed:
Thor
PS, this post is brought to you by the "Guns and Dope Party" and the "Bob for President" Foundation.
@ThorstenL Making low jitter divider with possibility of multiplex frequencies with selector is tricky 🤔
I2S specification does not state anything about the word length. Redbook CD requires bitrate of 44k1*16*2 = 1.4112MHz. The need for 32-bit word length comes from I2SoverUSB in this case.
Yes, I know all that. Remember I was lead on the team that delivered the first commercial 705.6/768k/DSD512 capable USB DAC using a DAC IC rated for "192kHz/DSD64".
But simultaneous mode output to TDA1541 should be MUCH LESS that 256 X Fbase.
If the designers make sense, 16 X Fsample, so 6.144MHz for 384kHz.
Even at 12.288MHz for 384kHz
Yes, I looked at these boards.
But as I need SPDIF in (WM8805 SW Mode) and did not want to mode switch on the fly between I2S and SIM I ruled it out and went with a USB Isolator PCB with ADUM 4166 & Amanero style XMOS together with CPLD PCB. This stuff:
All of it is still less than the JL Sounds board and ordering/shipping to Thailand was annoying for JLS, here Lazada is trivial, COD.
Thor
Well, if you carefully look at my table, if using BCK as clock source there is always enough extra "speed" for a fixed ratio and we can use MCK to reclock what comes out of our logic. So we work a fixed divider from BCK. Trivial.
Seeing how many people use FPGA/CPLD (where are the ARM Cortex CPU's including up sampling, digital filter options and full remastering suite? Guys, more imagination please) all of this is trivial.
Thor
I tried just capacitive coupling to p16, 17 similar to this (HtPierick circuit). It didn't work well for me. I was experiencing parasitic oscillations, so I switched to 10k + 2.2k to -15V
see post-7758328
Could you please elaborate on this? In this case it will do conversion during the pulse train (SIM mode). I'm not sure how it is important to convert during the bus silence but a common sense tells me that the less side activity on the chip during D/A conversion settling the better.
The circuit may need tuning. The 10K + 2.2k from John Brown is reliable, but throws extra switching noise into the TDA1541 oscillator pins and -15V. One reason is that there is a delay between Q and Qbar.
A better way to balance this would be a 74F86. And ideally we reference this to -15V and make a local 5V supply. In this case direct coupling works great, excessive swing may be usefully clipped with a pair of schottky signal diodes.
Or a CMOS to ECL converter IC or CMOS to LVDS could be used referenced to -15V.
onsemi MC100EPT20DR2G
For re-clocking the ECL flip-flop's are much better choice as well:
MC10EL31DR2G
Add the CMOS to ECL translator and you will be good to go.
Tubee's circuit should be oscillating at ~200kHz if you disconnect the two 1.2k Resistors. The capacitive coupling saves level translation.
The 1.2k resistors are for 5V logic and give basically 10V PP input to the resistive pad. You use 3.3V logic, so you need to adjust the pad.
Thor
SIM mode is about getting data in.
Originally there was no "out time"
I am not sure what this is meant to convey. What is "conversion"?
The TDA1541 internal logic is all NPN CML. It is very fast, maybe 1nS delay.
And has no appreciable noise, as it doesn't saturate active devices.
Once the data is latched to the input latch, LE transfers it to the Output Latch, see the block diagram:
The differential Latch drives a differential to SE driver that drive the bitswitch to +5V.
The switch is also not saturating (correct resistor value) and thus switches fast.
I think the entire state change on LE triggering happens in a few nS.
The setting time is simply down due to parasitic capacitances.
So I am not sure what " will do conversion during the pulse train" means and what it is meant to convey.
Once switches have switched, the system is in the new stable condition. Before the switches have switched, it is in the previous stable condition.
We switch from one bit pattern with one set of output switches to a new pattern. This is it. There is no "conversion".
You CANNOT "convert" during bus silence, because you do not "convert".
The input latch clock has no impact on the output latches or output switches.
Current mode logic (CML) needs differential signals to react, SE noise is rejected. It is not CMOS. And CML generally does not create any differential or common mode noise on either rails or radiated, again, because it all balanced and does not saturate devices or turn them off completely.
You might call it "Class A Logic". All devices always pass some current (hence the ridiculously high logic current of TDA1541).
It is what makes the TDA1541 truly unique among all DAC IC's available.
The one of the only sections where devices can saturate or turn off are the output Bitswitches. The diode connected npn transistors are reverse biased if the switch is activated and the NPN transistor that switches unused bit currents to +5V get's turned off (but is likely kept from saturating under on conditions).
The other part are the inputs. Here is my guess of the complete input circuit, which is TTL level to CML conversion:
T1 is subject to saturation if the input signal traverses a too wide range. How wide? MVAL tested, I did similar tests back for the CD-77 design:
Signals > 1.5V and < 1V saturate the input stage and make it clip. That throws noise into the rest of the circuit.
What is "during DA conversion". There is no such thing. It seems a concept applicable to SAR and pipelined ADC's is erroneously applied to DA circuits.
ALL Multibit DAC's have a set of latches somewhere and one latch is serial in parallel out, it holds the serial input data. On the correct WCK edge the content of this latch is transferred to a parallel in parallel out to parallel out latch, which drives the bit switches.
Within the speed limits of the logic used in the DAC, the "conversion" happens instantaneously as state change.
If you move the LE to just before the BCK train, all the various IC's in the system have settled to a "steady state" condition, all ground bounce has decayed to zero, everything is quiet, because it is static. This is the best chance to get your LE edge with the least possible timing uncertainty.
Anything that happens after that edge is deterministic and determined by circuit, bit clock or data will not affect it. even if the switching was slow enough, after the input stage has processed the edge the rest of the logic is differential and will not react to any noise from these sources.
However with the pulse train running, so to speak, ground bounce in IC's traversed, as well as in the TDA1541 input stage will cause level shift and trigger point uncertainty. This is why having the LE edge that triggers state change immediately after the BCK/Data part gives the greatest timing uncertainty for the system. Obvious really.
Thor