No, that would not work.
And it is not what I stated. I stated that the output current return's to +5V.
Not now, that is how the chip is designed.
No, the current "originates" from -15V and the current is 4mA.
The current switches per bit if the data is 0x0000 all send this current to +5V.
For any other input data, it will send a proportion of the current to +5V and the rest to Aol/Aor.
So the current in +5V is the inverse of Aol+Aor + Idigital (Idigital should be mostly constant) and thus variable with input data.
According to Mr Kirchhoff the sum of all currents in a given circuit node must be zero. If the current from Aol/Aor doesn't return to +5V the law is violated.
Alternatively we could state that the data dependent current from +5V returns to AGND and that data dependent currents from Aol/Aor must also return to AGNG.
The current physically doesn't return to ground. It has to flow through the +5V powersupply to balance the current difference in the +5V node.
Don't blame MVAL or me if you don't like it, take it up with Mr Kirchhoff.
His choices are absolutely responsible. He placed many large heat sources next to the DAC Chip. Do that, it gets hot.
It is not a "personal point". It's a fundamental natural law. As a result, "MUST".
It is not an "idea". After reviewing the known details on the internal schematic, the correct circuit node for DEEM capacitors is -15V.
If you do not connect them there, the current still needs to return there. It will do so through a less direct route.
They are connected via significant, frequency dependent (and often non-linear) impedances, so no, for AC purposes they are not directly connected.
Thor
Yup. Use some kapton and copper tape.
The kapton tape makes an isolation barrier, you then apply the copper tape to make a -15V plane under the TDA1541.
You then connect your bypass capacitors from DEEM pin to the copper foil plane connected to -15V.
Ideally, you also pull up the existing large value electrolytic capacitors and disconnect the "common" from AGND and make a connection to -15V.
Then the electrolytic capacitors are refitted with the common side (now -15V) negative and + towards the DEEM decoupling pin.
Now "fast" current glitches take the short expressway (toll road as we need to pay in parts and labour), slower changes take the county dirt road for free...
Thor
Thorsen, you understand that now , without any clear explanation , the only way to see if it is the way to go or not is to draw a pcb stackup ,build it , stuff it , measure it , listen to it and report , there is no way out 😎
my last build is made in a way I can connect by jumper the DEM cap return to + 15 v as it is now or - 15 v as you said , I will give it a try ( and make measurements ) and report here
I understand that you are totally convinced , and you are knowledgeable enough to be so , But I like all the theories to be true in the real world , would John and the Philips engineers didn't know about Kirchhoff laws 😳
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my last build is made in a way I can connect by jumper the DEM cap return to + 15 v as it is now or - 15 v as you said , I will give it a try ( and make measurements ) and report here
I understand that you are totally convinced , and you are knowledgeable enough to be so , But I like all the theories to be true in the real world , would John and the Philips engineers didn't know about Kirchhoff laws 😳
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I think it is absolutely clear.
Basic laws of physics are not subject to opinion or conviction.
They know of course. But most electronic engineers are what I'd call "ground focused".
The problem is, there is no ground.
Ground does not exist. It is a convention and fiction, which is useful when drawing schematics and if doing DC or very low frequencies is a sufficient approximation and classic RF construction actually manages the difference.
Because the non existent "ground" is incorrectly presumed to be 0 Ohm, 0 nH etc. or a close approximation (which it totally is not) engineers tend to return everything there and presume the differences just come out in the wash.
And as someone pointed out, a second also incorrect assumption is that power supply decoupling capacitors link all power supplies with zero impedance to the fictional ground.
In reality all that exists are current loops closed via non-zero impedances that cause non-zero error voltages to appear in the loops, whichay or may lead to unintentional and undesirable consequences.
Currents care nought about what you think, they just flow where they will based on the laws of physics.
Thor
What I think is none of importance , let see where they flow in this setup
I hope nobody says/think ground has no impedance , no inductance and so on , because it have some obviously
it is time now to make it real 😎
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Thorsen , as you already know you are here in a public forum , where people like to understand as much as they can , this is it ( no physic nobel here ) , what they understand the most is facts , based on builds , measurements , listenning sessions , and so on , this is what this place is all about
it doesn't mean theories are wrong , it means they should be proven each and every times
as I said before , lets do it .......
I remember one professor of mine , who says , it will be clear for me when you understand it as much as me............
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it doesn't mean theories are wrong , it means they should be proven each and every times
as I said before , lets do it .......
I remember one professor of mine , who says , it will be clear for me when you understand it as much as me............
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Hello Thorsten,
Not sure I understood well when we was talking briefly about the Grunding active DEM clock thing. This for the ones wanting to cope with >80K hz option :
"2) If using Fdeem > 80kHz the DEEM clock frequency must be synchronised with the word clock and must be AT LEAST 4 X word clock, top ensure all 4 current dividers are used for each sample."
Is this because beyond the internal oscillator it is divided by 4 , so minimal DEM clocking speed should be as per your illustration at minimum: 4 x44.1 = 176,4 K hz in order at minima NOS material works ?
This is acheived passive withe the external classic 470 pF or from any 4x oversampled Wordclock injected active to pin 16 (so sans cap), which is exactly what achieved Grunding CD with that option (x4 oversampling). Basicly Grunding active DEM is then : DEM clock = WCK.
But you say more in the phrase it should be 4x higher than WCLK. So using an oversampled material cause a pre filter or Audirnivana, HQ player, etc it means the DEM frequency should be 16 x 44.1 Hz ?
If I am not wrong this can be made by a shift register. I remember Pedja Rogic used that DEM sync with the BCK. But we could do that active with the Grunding scheme plus the shift register for elevation ? But for feeding the circuit it could not be from the -15V with the diode 5V1 diode of the G scheme because all should return to the -15V (I mean at the end the x14 DEM caps) ? (Does also Grunding shooted in their feet using the -15v as voltage source?😊
Btw, not related, but if choosing the first ground layer as -15V for the 14 DeEM caps sinking, what becomes the ground for decoupling the -15V powersupply and should it be tied to the TDA1541 DGND pin 14(this one goes to -15v layer now). ? I am not sure to understand where the AGND and DGND pins belong to which layer in your Layout road map ? AS the return layer of the outplug RCA ? AGND pin to 5V "powerrail-and-ground" idem for the gnd pin of the RCA ; DGND ? How to decouple atthe star ground meeting point ? (I do not understandcause I live still in the paradox of the basic inert ground layer all is analogic return path mantra 😆).
It could be safe to return the pin14 to the stat ground meeting point with an invidual trace on one of the ground layer or we forget it cause it will never be the same impedance/inductance than AGND pin anyway ? (Or make an independant trace below the ic between the two pins, but i fear the gnd loops at the end ?
Another topic we didn't talk yet is the difficulty to sync well the internal osci cause the difference between TDA1541As batch (exact value of the internal "cap-oscillator" ?; Does it matter or do we had to live with it and let the active DEM the sync choice as unique way (to sleep better) ?
Thanks again for the patience and didactic 🙂
Not sure I understood well when we was talking briefly about the Grunding active DEM clock thing. This for the ones wanting to cope with >80K hz option :
"2) If using Fdeem > 80kHz the DEEM clock frequency must be synchronised with the word clock and must be AT LEAST 4 X word clock, top ensure all 4 current dividers are used for each sample."
Is this because beyond the internal oscillator it is divided by 4 , so minimal DEM clocking speed should be as per your illustration at minimum: 4 x44.1 = 176,4 K hz in order at minima NOS material works ?
This is acheived passive withe the external classic 470 pF or from any 4x oversampled Wordclock injected active to pin 16 (so sans cap), which is exactly what achieved Grunding CD with that option (x4 oversampling). Basicly Grunding active DEM is then : DEM clock = WCK.
But you say more in the phrase it should be 4x higher than WCLK. So using an oversampled material cause a pre filter or Audirnivana, HQ player, etc it means the DEM frequency should be 16 x 44.1 Hz ?
If I am not wrong this can be made by a shift register. I remember Pedja Rogic used that DEM sync with the BCK. But we could do that active with the Grunding scheme plus the shift register for elevation ? But for feeding the circuit it could not be from the -15V with the diode 5V1 diode of the G scheme because all should return to the -15V (I mean at the end the x14 DEM caps) ? (Does also Grunding shooted in their feet using the -15v as voltage source?😊
Btw, not related, but if choosing the first ground layer as -15V for the 14 DeEM caps sinking, what becomes the ground for decoupling the -15V powersupply and should it be tied to the TDA1541 DGND pin 14(this one goes to -15v layer now). ? I am not sure to understand where the AGND and DGND pins belong to which layer in your Layout road map ? AS the return layer of the outplug RCA ? AGND pin to 5V "powerrail-and-ground" idem for the gnd pin of the RCA ; DGND ? How to decouple atthe star ground meeting point ? (I do not understandcause I live still in the paradox of the basic inert ground layer all is analogic return path mantra 😆).
It could be safe to return the pin14 to the stat ground meeting point with an invidual trace on one of the ground layer or we forget it cause it will never be the same impedance/inductance than AGND pin anyway ? (Or make an independant trace below the ic between the two pins, but i fear the gnd loops at the end ?
Another topic we didn't talk yet is the difficulty to sync well the internal osci cause the difference between TDA1541As batch (exact value of the internal "cap-oscillator" ?; Does it matter or do we had to live with it and let the active DEM the sync choice as unique way (to sleep better) ?
Thanks again for the patience and didactic 🙂
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This 14 Dem grounding suggestion is very interesting to me Iggy. In my early days of learning diy I truly thought
ground was ground. lol in reality as Thorsten mentioned there's no ground. Perhaps -15v could be left as a floating
supply. Thanks Thorsten for sharing your expertise & thoughts. Me have been mucking around the TDA for years,
always tweaking, learning & experimenting.
ground was ground. lol in reality as Thorsten mentioned there's no ground. Perhaps -15v could be left as a floating
supply. Thanks Thorsten for sharing your expertise & thoughts. Me have been mucking around the TDA for years,
always tweaking, learning & experimenting.
My dual 1541s are currently running with dem clock about 176k ie 4 x wck
I am experimenting with a Behringer 24/96 sample rate converter and when I send the dac 24bit 96Khz data, the distortion spectra is slighly worse.
Now I am wondering if it's Dem clock related as it's no longer 4 x wck.
I am experimenting with a Behringer 24/96 sample rate converter and when I send the dac 24bit 96Khz data, the distortion spectra is slighly worse.
Now I am wondering if it's Dem clock related as it's no longer 4 x wck.
No. It is because of the way Dynamic Element Matching (DEM) works. It is illustrated here:
This shows the MSB in detail.
Our reference current (Iref) is 4mA and is created by a current source referenced to -15V.
This current is split into 4 nominally equal currents of 1mA. In reality, as we find RJvdP's articles on TDA1540/1541 states that a maximum error of 5% is achieved in real IC's.
Clearly, 5% error is way, way outside what allows 16 or 14 Bit precision. The solution is the switching network, this is the actual "DEM".
The switches switch each of the 4 currents from the current splitter the 4 current outputs in order. So if we have a precise oscillator that gives each current source the same time, each current ON AVERAGE will be PRECISELY Iref / 4.
What happens next is that 2 current outputs from the switching network are combined to give the MSB (2mA) one current out becomes the next Bit (1mA) and the fourth current is again applied to a 4-Way current Splitter with DEEM; and again - for 3 cascaded DEM current splitters covering the 6 MSB.
The final leftover current is divided using multi-emitter transistors etc. to split the LSB(s) current of 1.25uA into the lowest 10 bit:
The external filter capacitors are in effect a moving average filter that holds the average of the currents. But it's a bit more interesting.
If we look at this circuit, we see an actual current source, where the current is determined by the voltage across the DEM Filter Capacitor and the resistor Rfil.
This is why "slow DEEM" actually can work. The capacitor will hold the voltage that is needed to make the average current from the switched diver flow in Rfil.
Hence the quip by MVAL that if the capacitor is infinite and ideal, once it is charged (which of course takes to the end of time) we can totally stop the DEM circuit.
So, we now have 16 binary weighted currents with 16 Bit accuracy, AS LONG AS our DEM oscillator is very stable and the value of our DEM filter/averaging capacitor is sufficiently large to hold it's charge long enough (say less than 0.5 or 0.25LSB change across a full 4 DEEM clock cycle).
A "trick" we can use is to synchronise the DEM clock with WCK so that the DEEM is at least 4 X WCK or an integer multiple), so that all 4 states of the DEM circuit happen within a single WCK / Sample.
In this case we can in theory get rid of the DEM filter capacitors completely, the current will be integrated in the capacitor across the current to voltage conversion resistor.
Here we arrive at possibly using lower value (10nF) capacitors and high DEM Clocks. We might use a ~6MHz bit clock to drive the DEM clock.
We just need to consider that everything now works at MHz and we need a suitable layout. Plus there is a caveat:
Higher DEM frequencies degrade THD &N at low frequencies, suggesting to me a lack of oscillator stability. It MAY not apply with an external synchronised clock.
Whatever WCK is supplied to TDA541 (which may be as high as 384kHz) DEM clock should be at least 4 times as much.
One option is we divide MCK to a fixed clock of 32X 44.1/48, but if my guess on the source of the THD/SNR degradation is is wrong, it would cause several dB loss in dynamic range.
The other option is to divide the BCK from ahead of I2S-2-SIM Board (which is 64 X WCK) by 16 and always get 4 X WCK.
If we use a 74XX74 as final 2 divider stages and to create a balanced drive to the TDA1541 oscillator, a 74AHCT74 (or 74ACT11074) gives divide by 4, so adding another 74XX74 divides BCK by 16 and gives a balanced output.
The Philips scheme used by Grundig causes current and noise leakage at Fdem. What recommends it only is simplicity. It is for easy retrofit and the improvement will outweigh the drawback.
Ok, le me restate the relevant pin pairs (or more).
The entire DEM circuit and current generation connects between AGND and -15V.
The digital circuit connects between -5V & +5V as it is differential but external inputs connects to DGND.
You can see the differential current mode logic driving the Bit switch.
Vref is +5V and the current sink under the differential pair is linked to -5V.
So one layer pair is AGND and -15V.
Another layer set is DGND with +/-5V.
Sadly +/-5V are not pure digital, so we also need to decouple to AGND. And DGND and AGND need to be linked from each kelvin point (sum of all currents = 0)..
No, the current loop for the RCA commonly does not include the TDA1541 at all.
I am not sure what this word salad means.
DGND is the reference for single ended input signals. Most logic is not connected to DGND, some is.
Several people have observed the oscillator is a bit jittery. When I simulated low frequency DEM relocking this was very visible. I suspect at the minimum Philips/Grundig sync should be used.
Thor
Some details relating to dem clock frequency in the attached pdf. Authors name isn't on it (wasn't me).
He cliaims dem clock needs to be much higher. (page 6)
I was also pondering on using dem capacitors of ten times lower value, eg 10n with a high dem clock frequency....
He cliaims dem clock needs to be much higher. (page 6)
I was also pondering on using dem capacitors of ten times lower value, eg 10n with a high dem clock frequency....
Yes. As said, I look logically to determine limits. It's my experience in general that faster clocks on DAC's cause degradation in HD. So all else equal we need at least 80kHz DEM clock. At that point we need fairly large value capacitor.
I think 1u/680n/470n/220n/100n/47n/47n would be fine for in this case a fixed DEM clock of 2 X Fs.
I do seem to remember John Brown testing with DEM = BCK (IIS mode) and not using any DEM Filtering (no caps).
You can try. Remember layout must be RF style.
Thor
I'm using one of my spare pcbs to rebuild using 1 0,22,.0.15, 0..033 0..033,8n2, 8n2 dem caps and 220pf dem clock capaciitor (~380Khz ie 4x 96kHz)
I found your I2S attenuator design but I only need to think about ground bounce because Ian Canadas I2S to PCM output is 3.3v so there is no supply rail bounce.
I found your I2S attenuator design but I only need to think about ground bounce because Ian Canadas I2S to PCM output is 3.3v so there is no supply rail bounce.
Hmmmm, do consider doing an clock external clock.
This is by John Brown originally. There is also DEM Synch from him.
I would no longer recommend this. I think the diode clipping circuit by MVAL is a better choice, especially if you can use my modification for better temperature tracking by directly sensing the TDA1541 temperature.
Thor
I was thinking about 3 germanium diodes to 0v with pullup resistors to keep the inputs around 0.4v) but will take a look at MVAL's.
@sumotan
When you say there are no ground you meant the pin 5 and pin doesn't have to be tied somewhere ?
Go try the sim mode you haven t yet in your long wise journey 🙂. You have several Aya biards to play with 😉
Have you a photograph of your 100 hz mode ? Me think you puttedthe lythic with long leads everywhere. Inductance ?????
Cheers Jaffrie.
When you say there are no ground you meant the pin 5 and pin doesn't have to be tied somewhere ?
Go try the sim mode you haven t yet in your long wise journey 🙂. You have several Aya biards to play with 😉
Have you a photograph of your 100 hz mode ? Me think you puttedthe lythic with long leads everywhere. Inductance ?????
Cheers Jaffrie.
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Well , I did measurements of returning the dem caps to -15 v ( and no where else ) like told by Thorsen at post 8723 versus returning to ground ( +15 v ) like it was before , and they speak by themself 😳
I have to say that my pcb is 4 layers , signal / ground / ground / signal + power , all layers are 1 oz of copper , it has been done HF like respecting all trace impedances 🙂
it is battery (lifepo4 ) powered with one battery for each voltage
DEM caps return to -15 v no signal
DEM caps return to ground no signal
DEM caps return to -15 v with signal
DEM caps return to ground with signal
measurements were made pcb out of the chassis
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I have to say that my pcb is 4 layers , signal / ground / ground / signal + power , all layers are 1 oz of copper , it has been done HF like respecting all trace impedances 🙂
it is battery (lifepo4 ) powered with one battery for each voltage
DEM caps return to -15 v no signal
DEM caps return to ground no signal
DEM caps return to -15 v with signal
DEM caps return to ground with signal
measurements were made pcb out of the chassis
.
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