pin4 does nothing in a tda1541a in i2s mode. You can connect it to anything. Gnd is probably best for performance.
I like the output current handling towards +5 and not gnd.
And the details on the handling of the i2s signals. I will make use of that in the future (for my private stuff)
Thanks for posting!
I like the output current handling towards +5 and not gnd.
And the details on the handling of the i2s signals. I will make use of that in the future (for my private stuff)
Thanks for posting!
I am going to try John's circuits, but feeding the TDA1541 with the I2S signal coming from a CS8412 receiver. Thus I have at hand the 2.8224 MHz (pin 12) and 11.2896 MHz (pin 19) clocks coming from the receiver. Can I use the 2.8224 MHz clock for DEM reclock, instead of the 1.4112 MHz one? Or is the frequency too high? Is there a way to obtain a 1.4112 clock from the CS8412?
How is the MCK clock used in John's circuit?
Sorry for the ingenuity of my questions.
Best regards.
Paul
How is the MCK clock used in John's circuit?
Sorry for the ingenuity of my questions.
Best regards.
Paul
I am using /2 (5.6448Mhz) for the DEM although from what I recall when this was being discussed, its pretty much the limit for DEM. It will work with some chips but not all. You will also need the inverse clock for the DEM if you are looking to implement the mod. You can use a gate to invert the clock signal.
/2 to pin 17, and inverted /2 to pin 16
It may be that there are gains discussed in the thread for using a lower DEM freq that I'm not aware of.
Ian
Hello EC,
I have a few questions if I may
I'm trying to do all these great mods in a cd player but there I have in NOS mode BCK at 2,8 Mhz (derrived from a MCLK divider), can I use the config posted by you using U5 to reclock this 2,8 Mhz BCK and then also feed this to the DEM pins? or this trick for the DEM with given component values will work only if BCK value is stricktly 1,4 Mhz?
I saw pretty different components and values used for I2S line attenuation and DJA used in your TDA1543 module that you posted earlier and this new TDA1541A mk2, is this I2S data stream needs to be treated different for the 2 DACs ?
I already ordered the components to try the discrete regulator schematic posted by you before for this application but maybe you can also show a simple schematic of your 3 stepped rectifier and capacitance multiplier used to feed this new mk2 DAC version with the +10V. -10V and -20V (I would be interested how it looks for the negative voltages)
I know that the classical 4 diode bridge rectifier if let's say we have a 9V AC voltage it gives 9V x square of 2 => 9V x 1.41 = 12.69 Vdc that enters smoothing caps and then regulators, but how is this value being calculated for
your 3 diode stepped rectifier? also what do you use for the actual capacitance multiplier, does it have something in common with the old schematic that used 2SK2391 ?
My last question has nothing to do with your project, but maybe I'll find the right answer.
I have a laptop which I would like to use with an external TDA1541 NOS DAC but if possible not through it's spdif output, so my question would be if I may use the I2S Data stream that goes to it's internal STAC9200 DAC (pin8) and
generate BCK and WS from an external 11,2896 MCLK to feed the TDA1541A DAC (all these only in 16/44 mode)?
Thanks in advance, maybe you'll have some time and patience to give some reply whenever is possible
I have a few questions if I may
I'm trying to do all these great mods in a cd player but there I have in NOS mode BCK at 2,8 Mhz (derrived from a MCLK divider), can I use the config posted by you using U5 to reclock this 2,8 Mhz BCK and then also feed this to the DEM pins? or this trick for the DEM with given component values will work only if BCK value is stricktly 1,4 Mhz?
I saw pretty different components and values used for I2S line attenuation and DJA used in your TDA1543 module that you posted earlier and this new TDA1541A mk2, is this I2S data stream needs to be treated different for the 2 DACs ?
I already ordered the components to try the discrete regulator schematic posted by you before for this application but maybe you can also show a simple schematic of your 3 stepped rectifier and capacitance multiplier used to feed this new mk2 DAC version with the +10V. -10V and -20V (I would be interested how it looks for the negative voltages)
I know that the classical 4 diode bridge rectifier if let's say we have a 9V AC voltage it gives 9V x square of 2 => 9V x 1.41 = 12.69 Vdc that enters smoothing caps and then regulators, but how is this value being calculated for
your 3 diode stepped rectifier? also what do you use for the actual capacitance multiplier, does it have something in common with the old schematic that used 2SK2391 ?
My last question has nothing to do with your project, but maybe I'll find the right answer.
I have a laptop which I would like to use with an external TDA1541 NOS DAC but if possible not through it's spdif output, so my question would be if I may use the I2S Data stream that goes to it's internal STAC9200 DAC (pin8) and
generate BCK and WS from an external 11,2896 MCLK to feed the TDA1541A DAC (all these only in 16/44 mode)?
An externally hosted image should be here but it was not working when we last tested it.
Thanks in advance, maybe you'll have some time and patience to give some reply whenever is possible
Hi ecdesigns,
First, please allow me to congratulate you for providing the full schematic of your TDA15410Mk2 DAC module. As others have already indicated, such generosity in revealing one's intellectual property is rare.
I notice in the schematic that you have the grounded-gate FET (T1, T2) output stages fed from the 7805 regulator (U3) +5V supply, via your super cool looking hand wound I/V resistors (R8, R9). I also note that you specify the output swing as 2Vpp which, of course, makes for an RMS output of only 0.7Vrms, well below the 2Vrms industry standard. No doubt, that low output amplitude is imposed by the 5V supply.
Have you considered feeding the I/V resistors from the 7915 regulator (U1) -15V supply? Of course, then, N-JFETs T1 and T3 would have to be replaced with P-JFETs (assuming suitable low Vg-s devices could be had). Also, R8 and R9 would need to be increased to nearly 1,500 ohms in order to produce an 2Vrms output amplitude.
Having read enough of your many previous design comments to doubt that you would have overlooked considering doing this, I'm going to risk guessing that the reason is the difficulty in nearly tripling the wire length to increase the resistance of R8 and R9 so much.
Best regards,
First, please allow me to congratulate you for providing the full schematic of your TDA15410Mk2 DAC module. As others have already indicated, such generosity in revealing one's intellectual property is rare.
I notice in the schematic that you have the grounded-gate FET (T1, T2) output stages fed from the 7805 regulator (U3) +5V supply, via your super cool looking hand wound I/V resistors (R8, R9). I also note that you specify the output swing as 2Vpp which, of course, makes for an RMS output of only 0.7Vrms, well below the 2Vrms industry standard. No doubt, that low output amplitude is imposed by the 5V supply.
Have you considered feeding the I/V resistors from the 7915 regulator (U1) -15V supply? Of course, then, N-JFETs T1 and T3 would have to be replaced with P-JFETs (assuming suitable low Vg-s devices could be had). Also, R8 and R9 would need to be increased to nearly 1,500 ohms in order to produce an 2Vrms output amplitude.
Having read enough of your many previous design comments to doubt that you would have overlooked considering doing this, I'm going to risk guessing that the reason is the difficulty in nearly tripling the wire length to increase the resistance of R8 and R9 so much.
Best regards,
ecdesigns,
Never mind my question, I believe that I've just found the answer myself. I haven't personally designed with the TDA5141A, but in looking again at your DAC module schematic I realize that the TDA1541A must have an internal current-source which sinks the output stage quiescent bias current to ground. My suggestion to invert the output stage topology to operate from the -15V supply would then require inclusion of an external current-source to bias the P-JFET based common-gate output stage.
Sorry for the bother.
Never mind my question, I believe that I've just found the answer myself. I haven't personally designed with the TDA5141A, but in looking again at your DAC module schematic I realize that the TDA1541A must have an internal current-source which sinks the output stage quiescent bias current to ground. My suggestion to invert the output stage topology to operate from the -15V supply would then require inclusion of an external current-source to bias the P-JFET based common-gate output stage.
Sorry for the bother.
To quote Henk from the 1541 info thread:
The inner circuit of the dac can be seen as a binairy controlled differential stage. One output (the not used) flows in pin 28, thus +5V. The outher output in pin 6, 25. The sum of signal currents in pin 6, 25 and pin 28 is constant. That means that it is advantageous to bring the output currents in pin 6, 25 back into the +5V supply.
The thread also contains the info on DEM reclocking and I2S inputs.
And more..
The inner circuit of the dac can be seen as a binairy controlled differential stage. One output (the not used) flows in pin 28, thus +5V. The outher output in pin 6, 25. The sum of signal currents in pin 6, 25 and pin 28 is constant. That means that it is advantageous to bring the output currents in pin 6, 25 back into the +5V supply.
The thread also contains the info on DEM reclocking and I2S inputs.
And more..
@luxury
that chip STCA is from apple hardware
but only one version, i think 9003 version have I2S pins...
please read in the PDF
.
I modified one macMini from the friend, to have coax from optical
spdif and find that chip inside
it is for my opp. and exp. best digi out...
.
cheers
and prepare for the really small hardware
that chip STCA is from apple hardware
but only one version, i think 9003 version have I2S pins...
please read in the PDF
.
I modified one macMini from the friend, to have coax from optical
spdif and find that chip inside
it is for my opp. and exp. best digi out...
.
cheers
and prepare for the really small hardware
Question about DJA
Hello John,
First, I would thank you to share your design to us.
It's great as alway. Well, I'm so wonder the term -DJA-, dynamic jitter attenuator, and have some questions.
From shcematic and explanation in post #3335. Could you please explain how DJA work? Seem DJA apply on both sine and square wave in your schematic. Why jitter have to be attenuated and What's benefit of DJA? How to apply DJA to other sampling rate such as 96kHz or 192kHz? So many questions but please. Thanks for your kind.
Regards,
Art.
Hello John,
First, I would thank you to share your design to us.
It's great as alway. Well, I'm so wonder the term -DJA-, dynamic jitter attenuator, and have some questions.From shcematic and explanation in post #3335. Could you please explain how DJA work? Seem DJA apply on both sine and square wave in your schematic. Why jitter have to be attenuated and What's benefit of DJA? How to apply DJA to other sampling rate such as 96kHz or 192kHz? So many questions but please. Thanks for your kind.
Regards,
Art.
Some questions about the schematic in post #3335:
1) I was not able to find a source, and neither the datasheet, of the 74G79 chip (U6 and U7 in the schematic).
Could anyone provide some information about this IC?
2) the attenuator of the WSO and DSO signals have not a pull-up resistor, as is in previous versions of the I2S attenuator. Does this relate to the characteristics of the 74G79 chip? What values should be used for R10, R11, R13, R14 if a 74HCT74 chip is used for U6 and U7?
3) My NOS DAC uses a CS8412 receiver. Is it possible to derive the DEM clock from the 2.8224 MHz coming from pin 19 of the receiver? Is it advisable to divide this signal by 2 for use as a DEM clock?
Best regards.
Paul
1) I was not able to find a source, and neither the datasheet, of the 74G79 chip (U6 and U7 in the schematic).
Could anyone provide some information about this IC?
2) the attenuator of the WSO and DSO signals have not a pull-up resistor, as is in previous versions of the I2S attenuator. Does this relate to the characteristics of the 74G79 chip? What values should be used for R10, R11, R13, R14 if a 74HCT74 chip is used for U6 and U7?
3) My NOS DAC uses a CS8412 receiver. Is it possible to derive the DEM clock from the 2.8224 MHz coming from pin 19 of the receiver? Is it advisable to divide this signal by 2 for use as a DEM clock?
Best regards.
Paul
Hi Sandor,
STMICROELECTRONICS|74V1G79CTR|LOGIC, 74V1G, D-TYPE FLIP-FLOP | Farnell Nederland
This is a different I2S attenuator / rectifier circuit, it is not related to the 74V1G79 chip.
I strongly advise not to use a 74HCT74 chip for synchronous reclocking. It has on-chip crosstalk between flip-flops (high jitter) and HCT series has too high propagation delay.
It's better to use separate flip-flops (one flip-flop in one housing). Apply suitable power supply filtering for each flip-flop. Use fastest available logic that can handle the required signal and power supply levels. These offer shortest propagation delay and lowest jitter. Also minimize connected load capacitance as increasing load capacitance increases propagation delay. This requires very short wiring and suitable attenuators that reduce the effects of load capacitance.
The DEM clock can be derived from the 2.8224 MHz by using a flip flop with both, Q and /Q outputs. The following flip-flop works fine:
ON SEMICONDUCTOR|NL17SZ74USG|SINGLE D FLIP FLOP, SMD | Farnell Nederland
CS8412 doesn't attenuate source jitter much, so suitable reclocking with an external low jitter clock is required.
STMICROELECTRONICS|74V1G79CTR|LOGIC, 74V1G, D-TYPE FLIP-FLOP | Farnell Nederland
This is a different I2S attenuator / rectifier circuit, it is not related to the 74V1G79 chip.
I strongly advise not to use a 74HCT74 chip for synchronous reclocking. It has on-chip crosstalk between flip-flops (high jitter) and HCT series has too high propagation delay.
It's better to use separate flip-flops (one flip-flop in one housing). Apply suitable power supply filtering for each flip-flop. Use fastest available logic that can handle the required signal and power supply levels. These offer shortest propagation delay and lowest jitter. Also minimize connected load capacitance as increasing load capacitance increases propagation delay. This requires very short wiring and suitable attenuators that reduce the effects of load capacitance.
The DEM clock can be derived from the 2.8224 MHz by using a flip flop with both, Q and /Q outputs. The following flip-flop works fine:
ON SEMICONDUCTOR|NL17SZ74USG|SINGLE D FLIP FLOP, SMD | Farnell Nederland
CS8412 doesn't attenuate source jitter much, so suitable reclocking with an external low jitter clock is required.
As I understand, the re-clock oscillator only makes sense if it clocks the source too, i.e. if it is the master clock of the whole digital chain.
I use a media server as a source. This device only has a spdif digital output and the I2S signals for the TDA1541A are provided by a CS8412 receiver. I am not willing to modify the media server to accept an external master clock.
Do you see any good reason to use an external oscillator?
Best regards.
Marco
I use a media server as a source. This device only has a spdif digital output and the I2S signals for the TDA1541A are provided by a CS8412 receiver. I am not willing to modify the media server to accept an external master clock.
Do you see any good reason to use an external oscillator?
Best regards.
Marco
Hi Sandor,
Placing the clock (and synchronous I2S reclockers) close to the DAC chip and slaving the source is perhaps one of the best methods for achieving low jitter.
I didn't realize this at first, but all I2S signals need to have lowest possible jitter too, not only the signal that determines sample timing. This is mainly due to crosstalk between I2S input signals and the analogue DAC outputs.
Then it's going to be extremely difficult to extract low jitter I2S signals. However, it is possible to slave a squeezebox media player.
When using I2S straight from the CS8412 you have the guarantee that you end up with high jitter levels in the region of 500ps ... 1ns rms typical. Even for NOS, jitter levels need to be a fraction of this.
Now you got some options:
- Asynchronous reclocking (ASRC).
- PLL / VCXO combination.
- VCXO-based digital PLL / frequency tracker.
In my humble opinion, nothing beats a straight-forward clock circuit (local clock), slaving the source.
Placing the clock (and synchronous I2S reclockers) close to the DAC chip and slaving the source is perhaps one of the best methods for achieving low jitter.
I didn't realize this at first, but all I2S signals need to have lowest possible jitter too, not only the signal that determines sample timing. This is mainly due to crosstalk between I2S input signals and the analogue DAC outputs.
Then it's going to be extremely difficult to extract low jitter I2S signals. However, it is possible to slave a squeezebox media player.
When using I2S straight from the CS8412 you have the guarantee that you end up with high jitter levels in the region of 500ps ... 1ns rms typical. Even for NOS, jitter levels need to be a fraction of this.
Now you got some options:
- Asynchronous reclocking (ASRC).
- PLL / VCXO combination.
- VCXO-based digital PLL / frequency tracker.
In my humble opinion, nothing beats a straight-forward clock circuit (local clock), slaving the source.
Thank you very much John.
Maybe for a while I will live with the high jitter coming from the CS8412.
(by the way, I'm skeptical towards ASRC though, honestly, I have never tried it).
Now for some more questions:
1) May I use the attenuation scheme in your post #3335 to feed the TDA1541A with the WS and DATA signals coming from CS8412 (obviously no U6-U7)? Which values should I use for R10-R11 and R13-R14?
2) I will use the BCK signal to derive the DEM clock. Should I connect the BCK from CS8412 to CP of U5?
2) Is it better to use a 1.4112 MHz clock to derive the DEM clock? To this end I could connect D to not-Q of U5 to divide BCK by 2. In this case which attenuator circuit could I use to connect BCK to the TDA1541?
Best regards.
Paul
Maybe for a while I will live with the high jitter coming from the CS8412.
(by the way, I'm skeptical towards ASRC though, honestly, I have never tried it).
Now for some more questions:
1) May I use the attenuation scheme in your post #3335 to feed the TDA1541A with the WS and DATA signals coming from CS8412 (obviously no U6-U7)? Which values should I use for R10-R11 and R13-R14?
2) I will use the BCK signal to derive the DEM clock. Should I connect the BCK from CS8412 to CP of U5?
2) Is it better to use a 1.4112 MHz clock to derive the DEM clock? To this end I could connect D to not-Q of U5 to divide BCK by 2. In this case which attenuator circuit could I use to connect BCK to the TDA1541?
Best regards.
Paul
Last edited:
Hi Sandor,
You will need to adapt WS / DATA attenuators for 5Vpp: R10,R11 = 820R, R1,R14 = 1K.
Yes, but you have to configure U5 for divide-by-two circuit: CP(1) goes to CS8412 BCK output, D(2) goes to /Q(3). Both outputs, Q(5) and /Q(3) can now be used to synchronize the DEM clock circuit on the TDA1541A.
The DJA (D3 ... D5, R1, R5, R6, and C26) also connects to the CS8412 BCK output. BCK output of the CS8412 goes to anode of D5. Since the DJA was designed for 4V operation, R6 value needs to be lowered to approx. 220R for 5V operation.
here is an article about jitter reduction:
welcome to www.jitter.de
You will need to adapt WS / DATA attenuators for 5Vpp: R10,R11 = 820R, R1,R14 = 1K.
Yes, but you have to configure U5 for divide-by-two circuit: CP(1) goes to CS8412 BCK output, D(2) goes to /Q(3). Both outputs, Q(5) and /Q(3) can now be used to synchronize the DEM clock circuit on the TDA1541A.
The DJA (D3 ... D5, R1, R5, R6, and C26) also connects to the CS8412 BCK output. BCK output of the CS8412 goes to anode of D5. Since the DJA was designed for 4V operation, R6 value needs to be lowered to approx. 220R for 5V operation.
here is an article about jitter reduction:
welcome to www.jitter.de