Re: Re: Re: Re: Re: Re: EC problems.
If both the standing current and the value of the collector resistors of the EC diff pair transistors are high enough to cope with the rise in Vgs of the your output MOSFETs (and the comparatively small loss of the BJT driver stage) for a given output current, then the EC transistors simply will not cut off.
It's as simple as that. If you were to leave your design as is, except for the addition of another pair of MOSFET output devices to increase the output power and peak load current, the EC circuit would have a much lesser maximum Vgs to deal with, so in effect the EC transistors will be driven even less close to cut off.
Mikes' claim the EC loops are only usefull for low-moderate power outputs is baloney.
I've developed the above EC scheme, albiet modified, for the class A output stages of my rail-tracking 500W class A amp. The EC circuit takes its power from fixed regulated rails with the output devices (High fT Sanken BJT's) and driver devices powered from the output tracking +/- 10V unregulated rails.
The EC loop doesn't begin to run into problems until the load resistance is sufficently low to induce an output current of over 150A at peak voltage output (at which point the EC transistors run out of voltage headroom); and contrary to a previous assertion, Iq of the output stage has absolutely nothing whatever to do with it.
Cheers
Glen
Bob Cordell said:
If both the standing current and the value of the collector resistors of the EC diff pair transistors are high enough to cope with the rise in Vgs of the your output MOSFETs (and the comparatively small loss of the BJT driver stage) for a given output current, then the EC transistors simply will not cut off.
It's as simple as that. If you were to leave your design as is, except for the addition of another pair of MOSFET output devices to increase the output power and peak load current, the EC circuit would have a much lesser maximum Vgs to deal with, so in effect the EC transistors will be driven even less close to cut off.
Mikes' claim the EC loops are only usefull for low-moderate power outputs is baloney.
I've developed the above EC scheme, albiet modified, for the class A output stages of my rail-tracking 500W class A amp. The EC circuit takes its power from fixed regulated rails with the output devices (High fT Sanken BJT's) and driver devices powered from the output tracking +/- 10V unregulated rails.
The EC loop doesn't begin to run into problems until the load resistance is sufficently low to induce an output current of over 150A at peak voltage output (at which point the EC transistors run out of voltage headroom); and contrary to a previous assertion, Iq of the output stage has absolutely nothing whatever to do with it.
Cheers
Glen
Re: Re: Re: Re: Re: Re: Re: EC problems.
Incidentally, that's only in simulation. In real life, the BJT's would start emiting smoke at that kind of current. 🙂
G.Kleinschmidt said:
Incidentally, that's only in simulation. In real life, the BJT's would start emiting smoke at that kind of current. 🙂
I have built a small gain stage with voltage gain of about 25.
This is simple and relatively dirty one, but uses something like Hawksford's error correction over a whole gain stage and it works!!
I'll measure it at wendesday, so that I will be able to tell more (stability, distortion).
But the moral is that this is certaily doable to cancel distortion in Hawksford's style of a whole amplifier circuit, not only output buffer.
cheers
This is simple and relatively dirty one, but uses something like Hawksford's error correction over a whole gain stage and it works!!
I'll measure it at wendesday, so that I will be able to tell more (stability, distortion).
But the moral is that this is certaily doable to cancel distortion in Hawksford's style of a whole amplifier circuit, not only output buffer.
cheers
Re: Re: Re: Re: Re: Re: Re: EC problems.
Thanks Glen. I agree. I don't recall exactly, but I think I sized the EC circuit to be able to deliver a forward gate bias to the MOSFETs in excess of about +8V (which corresponds to a lot of amps, even with only one device). You're right, an amplifier with a paralleled pair of output devices would need even less EC headroom.
Cheers,
Bob
G.Kleinschmidt said:
Thanks Glen. I agree. I don't recall exactly, but I think I sized the EC circuit to be able to deliver a forward gate bias to the MOSFETs in excess of about +8V (which corresponds to a lot of amps, even with only one device). You're right, an amplifier with a paralleled pair of output devices would need even less EC headroom.
Cheers,
Bob
mikeks said:
True in part, as already noted here.
Of academic interest, however, as the output stage goes into voltage clip, the EC BJTs tend to be driven into saturation (forward-biased collector-base junctions).
There is no evidence of sticking in this amplifier as a result of such asserted saturation. If there is no sticking, such saturation is of no consequence. Although not directly related, the use of the Baker clamps on the VAS play a big role in the prevention of sticking in this amplifier when it clips.
Glen's point stands.
Bob
Bob Cordell said:
Actually, I was referring to the output stage being driven to clip in general; EC transistors tend to be driven into saturation in those circumstances; I did not refer to a specific amp design.
darkfenriz said:
Bandwidth - 700kHz (-3dB)
Nulling test using a scope showed basically noise and scope trigger artifacts.
Square wave response at 100kHz was nearly perfect, settling time well below 5% of cycle, but with little overshoot when close to clipping.
This data does not indicate that's wonderful performance, but this is clearly a nice technique to use and giving non-sub-optimal results.
G.Kleinschmidt said:
I think the word you're looking for is well-founded "debate", as opposed to idle speculation.🙂
mikeks said:
“Well-founded debate” is three words. Also, the single word “debate”, used as a description of what you are attempting instigate, does necessarily imply “well-founded”. As a consequence of the latter, I have no qualm with your usage of the word per se.
D'oh!
“Well-founded debate” is three words. Also, the single word “debate”, used as a description of what you are attempting instigate, does not necessarily imply “well-founded”. As a consequence of the latter, I have no qualm with your usage of the word per se."
I stuffed up my gibberish.
“Well-founded debate” is three words. Also, the single word “debate”, used as a description of what you are attempting instigate, does not necessarily imply “well-founded”. As a consequence of the latter, I have no qualm with your usage of the word per se."
I stuffed up my gibberish.
