estuart said:
As a matter of fact I prefer CFP output stages for the voltage gain they can provide (2x - 3x is enough), in turn allowing driver to work at a lower voltage than power rails. This makes possible use of high performance wideband drivers (usually modern audio OpAmps) making for relatively simple and compact designs.
For all this to make sense, and being serious loop gain and feedback in the output stage, wideband power devices are a must in my view, which in turn tips the scales toward power MOSFETS, though of course this may be arguable.
Rodolfo
About Q8 in the circuit from my 1996 article:
One of the outputs of the amplifying current mirror was made with two PNP transistors rather than one, because otherwise the power dissipation would become a bit high for a single BC556 or BC560 or whatever. That the only reason why I put Q8 in the circuit. I'm sure it has its own emitter resistor, not just an RC series branch.
Best regards,
Marcel van de Gevel
One of the outputs of the amplifying current mirror was made with two PNP transistors rather than one, because otherwise the power dissipation would become a bit high for a single BC556 or BC560 or whatever. That the only reason why I put Q8 in the circuit. I'm sure it has its own emitter resistor, not just an RC series branch.
Best regards,
Marcel van de Gevel
ingrast said:
Hi Rodolfo,
Probably, we are on the same track. To confirm this, shall we exchange our schematics? Preferably by e-mail, as mine isn't bullet proof yet.
Cheers,
estuart said:
Hi Rodolfo,
Probably, we are on the same track. To confirm this, shall we exchange our schematics? Preferably by e-mail, as mine isn't bullet proof yet.
Cheers,
The output stage I am using is the one posted in the earlier link and has baged probably over 600 trouble free listening hours spread among several amplifiers, though I do not claim it to be bullet proof to be sure. The remainder I cannot publish for the time being, hope to be able soon. My mailing address is ingrast@adinet.com.uy.
Rodolfo
By the way, about the compensation capacitors in my circuit: its a long time ago, but I think I got a bit of overshoot on the non-linear common-mode loop square wave response and it looked cleaner with the capacitors.
I agree that the non-linear common-mode loop has to be fast compared to the differential loop. That is why I used as simple a loop amplifier as practicable and only a very subtle frequency compensation. Two of the capacitors only decouple diode-connected transistors that are supposed to have constant base-emitter voltages anyway. The other two provide a small zero by reducing the local feedback in the amplifying current mirror. They aren't made higher than necessary to get rid of the overshoot.
Best regards,
Marcel
I agree that the non-linear common-mode loop has to be fast compared to the differential loop. That is why I used as simple a loop amplifier as practicable and only a very subtle frequency compensation. Two of the capacitors only decouple diode-connected transistors that are supposed to have constant base-emitter voltages anyway. The other two provide a small zero by reducing the local feedback in the amplifying current mirror. They aren't made higher than necessary to get rid of the overshoot.
Best regards,
Marcel
MarcelvdG said:
Hi Marcel,
I beg to slightly disagree on this point. Admittedly I have not pursued further with analysis and/or simulations with this circuit, but I guess C39/C40 cannot be considered merely bypass capacitors. That in fact should be negating the active feedback at high frequencies required to prevent full cutoff during the reverse cycle.
Again, I have no time to analyze this in depth so I may be wrong, may be someone lurking here 😉 whose nickname starts with A and ends with _c may ..aheem.. rise to the challenge?
Rodolfo
Upon a second look, it seems the intention with Q2/Q4 was to provide a constant voltage reference, being the signal chain Q1-Q5-Q6 / Q3-Q5-Q7 for each polarity.
Rodolfo
Rodolfo
ingrast said:
Thanks Rodolfo.
And here is my basic O/P stage. Notice the common mode control loop (Q13...Q21), holding Ig at 125mA. As one can see, this loop is based on the design by Marcel van de Gevel.
Also notice that this schematic is FAR from complete. No I/P stage, no compensation, no clamps no protection etc.
Cheers,
Bob Cordell said:
Hi Bob,
just to illustrate that your assumpton was incorrect, I attach here another graph made from the same data, but showing how the input capacitance corresponds to the drain current for a constant 5V drain voltage. As you may see now clearly the "jump" occurs between 1 and 30 mA and that is most certainly is the beginning of the operation above the threshold.
Cheers
Alex
estuart said:
Edmond,
Upon a cursory examination, it is not clear to me how current is controled during the opposite cycle for this arrangement.
I guess from the schematic appearance your are using Microcap, it should be interesting to plot device current at various frequencies.
Rodolfo
estuart said:
estuart said:
Hi Glen,
I've 'slightly' modified your design: cascade transistors removed and used for other tasks:
1. Nested differential feedback (Q19/20)
2. Common mode control loop VAS ((20/21 and Q27/28)
3. VAS over current protection (Q23/24)
Other modifications:
4. Transitional Miller compensation (C19, R47)
5. Input clamp (D1/2)
6 Temperature compensation ((D5...D7)
Simulated specs are not as good as a Halcro, but probably you can't hear a THD20 of 0.8ppm.
Look below for the circuit diagram:
Cheers,
ingrast said:
Hi Rodolfo,
I'm not sure what you mean by "opposite cycle" , but I assume discharging of one of the gates. As for the "top half", current mirror Q9/Q10 can sink and source quite a hefty amount of current.
Alas, the common control loop can't supply that much, as the current mirror is only biased with 2*5 = 10mA.
I hope I've answered your question, else please specify which device currents you like to see.
Cheers,
PS: I'll be back within 2 hours.
estuart said:
Drain current in this case for each output device during the inactive half period. It is supposed to never drop to 0.
Rodolfo
ingrast said:
Hi Rodolfo,
The first graph shows the transient response at 10kHz and C42=c42=0. As you can see, during "turn off", Id never drops below about 40mA. In the next post C42=42=3n3, so the idle current behaves a little bit different.
Cheers,
ingrast said:
And here is the 2nd graph. C42/C43 has been made 3n3 to improve the step response.
Cheers,
x-pro said:
Hi Alex,
I don't think I made any wrong assumptions, but things are a matter of degree. The spec sheet I have for this device shows very little, but it does specify a threshold around 1 V, so I was correct in stating that the jump occurs well above threshold.
One has to recognize that this is a device with a rated Rds on of 50 ohms. I believe that if you re-run your test at a Vds of 10V, you will see the knee of the capacitance curve vs current move out accordingly.
The effect you are talking about is real (input capacitance increasing as the device approaches the triode region), but it needs to be put into context and perspective. Get yourself an IRFP240 and do the test, and you will see that the IRFP240 reaches well into the ampere region by the time its input capacitance has doubled if you put, say 10V across it. Well-designed amplifiers obviously have to cope with device capacitances that may double over their various different operating points, but this is not the serious problem you make it out to be (except for designers who don't know what they are doing).
Cheers,
Bob
estuart said:
Fine, this is how my output stage works also, only there are no compensation capacitors.
Your challenge now is to add overload protection and perhaps look for ways of making the whole job simpler cutting on component count if possible.
Rodolfo