Re: Re: Re: Your Statement is self contradictory....
[OFF]Well, you were speaking about self-contradictions...
[/OFF]
Alex
Workhorse said:
Nikitin, Do you feel like Trapped in your own statement....
Are you feeling Itchy....!
BTW: I donot like off-topic posts and personal attacks isn't my intention......
[OFF]Well, you were speaking about self-contradictions...
[/OFF]Alex
AndrewT said:
x-pro said:
I'll try to address both of these concerns. I'm familiar with the problems of the standard SPICE NMOS and PMOS models regarding the junction capacitances. Specifically, those models simulate the junction capacitances as being constant with voltage. But the model I'm using is one that's unique to LTSpice and specifically created to model vertical MOSFETs. It is called VDMOS and its description can be found in the LTSpice documentation. It uses a special formula to fit the nonlinear gate-drain capacitance vs. voltage. In order to fit the parameters to the datasheet graphs, I'm using the Excel solver to do a nonlinear least squares curve fit. That technique is described in this post. The models that I used in my simulation were fit to the datasheet graphs by me. The Excel spreadsheet in the zip file attachment of that post shows, among other things, a graph comparing the datasheet junction capacitances with the capacitances predicted by the formula that's in the LTSpice VDMOS documentation referenced above.
To answer AndrewT's question, the input capacitance could be approximated using this technique, but as PMA mentioned, it depends on the load. It also depends on the input voltage applied to the gate. The capacitance gets higher as the input approaches either rail. In a feedback amplifier design, this means that the amp gets less stable as clipping is approached.
One might also question whether the comparison is fair regarding the BJT models, and whether they fit their datasheet parameters. The BJT models I used were also fit to the datasheet by me, as the OnSemi models for these are way off. The technique for doing that is described here. I've attached my simulation files to this post in a zip file.
andy_c said:
Andy, you've misunderstood what I've said. It is not about Cgd, but about Cgs. Try to simulate a very simple circuit - charging the gate of the MOSFET by a CCS, say 50uA over 1ms (at low Vds=1V) - it will give you 50 nQ gate charge. If the model is correct, you should observe a curve close to one in the datasheet with a flat part near the threshold voltage. Your model does not do it. On top of it, this curve changes with Vds as well. I did some interesting measurements on this, however the data is on my office machine and I would be able to post it only tomorrow.
Note: only a fraction of this added gate charge at Vth is due to the Miller charge.
Cheers
Alex
Alex,
Your test circuit is wrong.
I've attached the gate charge sim from Hendrik Jan Zwerver of the LTSpice Yahoo user's group. He created the VDMOS model extraction program (which I did not use). Be sure to use the attached plot settings file to view the graph. You'll notice the gate charge graph matches the datasheet very closely.
Your test circuit is wrong.
I've attached the gate charge sim from Hendrik Jan Zwerver of the LTSpice Yahoo user's group. He created the VDMOS model extraction program (which I did not use). Be sure to use the attached plot settings file to view the graph. You'll notice the gate charge graph matches the datasheet very closely.
andy_c said:
Andy,
there is nothing wrong with my circuit
. However the circuit by Hendrik just creates very special conditions so the model and the datasheet info would match. It has nothing to do with an actual behaviour of a real MOSFET near the threshold. In Hendrik's simulation ALL of the additional charge is created by Miller effect, however for a real MOSFET only a part of it (and a smaller part) is a Miller charge. In a real device you would observe a similar curve even if there is no voltage on the drain and no current through at all , or if a Vds is not changing - as it is in my circuit. And that makes a lot of difference in an amplifier simulation. You'll see what I mean when I post my measurements tomorrow.Cheers
Alex
x-pro said:there is nothing wrong with my circuit
Looks like he's just matching the conditions of how the device was actually tested per the datasheet, with the 11A current source and so on. Your circuit isn't doing that, so I have no reason to believe the results would look like the datasheet at all. Everything that Hendrik is doing seems to correspond exactly to the IRF app note AN-944. Your explanation seems to contradict AN-944.I didn't attempt to fit the gate charge curves to the datasheet. I just matched the capacitances. But it doesn't surprise me that the gate charge curves match the datasheet. It's just two different ways of looking at the same thing.
andy_c said:
I didn't attempt to fit the gate charge curves to the datasheet. I just matched the capacitances. But it doesn't surprise me that the gate charge curves match the datasheet. It's just two different ways of looking at the same thing.
Andy,
what I am trying to say is that the MOSFET models (like the one for IRFP244) do not represent faithfully actual physical processes in a device and the result could be very misleading. I did actual measurements of the gate capacitance v gate-source voltage on a couple of FETs - just to confirm a well known effect of a gate-channel capacitance increase near the threshold and my results clearly show that most of the charge on a "flat" part of the curve is due to the Cgs charge, and not due to the Cgd charge, as shown on Hendrik's simulation diagram. I'll find tomorrow some other datasheets where this effect is properly represented.
This particular deficiency of common MOSFET models is a serious problem in an analogue simulation.
Cheers
Alex
andy_c said:
Very good post, Andy. Earlier in the thread I was wondering if the superior LTSpice model was being used. LT Spice is an exceptional simulator, and even more exceptional in that it is free.
I am amazed at how many people complain about the so-called high capacitances of vertical MOSFETs and don't realize the high capacitances that also exist, and are also nonlinear, in bipolar power transistors, especially the incredibly high base-emitter capacitance of the device when it is turned on and conducting current.
Bob
Just to be sure we're talking about the same thing, have a look at the IR AN-944. See figure 4 of that app note. The flat portion of the gate charge curve begins when the value of Vgs is such that Id = 11A on the Id vs. Vgs curve of the IRFP244. The diode across the current source of Figure 4 of AN-944 turns off at this time, and the drain voltage begins to ramp down. So Vgs is a little over 7V (Figure 3 and Figure 6 of the IRFP244 datasheet). If Id were independent of Vds, the "flat" portion would be truly flat. Suppose it were actually flat. Then Vgs would not change in this region. If that's the case, then no increase of charge to Cgs would occur. The charge would have to be going somewhere else - namely the gate-drain capacitance.
What you're talking about is a nonlinear Cgs vs Vgs. If that were the case, the symptom would not be in the "flat" region at all, but in the initial "ramp up" region. What you'd see in the ramp-up region would not be a straight line, but a curve. The flat region of the curve is flat because the drain current is no longer ramping up - it's reached the constant value of the current source, turning the diode off (Figure 4 of AN-944). If the effect you're seeing is near the threshold voltage as you say, the symptom would be way before the flat region. It would be at a Vgs value somewhat less than 4V - putting it clearly in the first region.
If Cgs varies with Vgs as you say, I agree that it's important to analog simulation. But I don't think it's related to the gate charge curve in the way that you say it is. In fact, the initial ramp-up appears quite linear according to the datasheet. So for the IRFP244, I'd conclude that it's not a significant consideration.
What you're talking about is a nonlinear Cgs vs Vgs. If that were the case, the symptom would not be in the "flat" region at all, but in the initial "ramp up" region. What you'd see in the ramp-up region would not be a straight line, but a curve. The flat region of the curve is flat because the drain current is no longer ramping up - it's reached the constant value of the current source, turning the diode off (Figure 4 of AN-944). If the effect you're seeing is near the threshold voltage as you say, the symptom would be way before the flat region. It would be at a Vgs value somewhat less than 4V - putting it clearly in the first region.
If Cgs varies with Vgs as you say, I agree that it's important to analog simulation. But I don't think it's related to the gate charge curve in the way that you say it is. In fact, the initial ramp-up appears quite linear according to the datasheet. So for the IRFP244, I'd conclude that it's not a significant consideration.
andy_c said:
Andy,
I've seen that appnote and some more here:
http://www.fairchildsemi.com/an/AN/AN-7502.pdf
which just shows that this process is not an easy thing to model.
However all these approaches are concerned only with a switching of a MOSFET on and off, not with it's behavior in a linear application. And it you look at a MOSFET from a linear point of view the picture is quite different. The effect I'm talking about is well known to IC designers as many modern opamps are using MOSFET technology. I've decided to check if the same effect is well pronounced in power devices and my measurements indicate that it is indeed the case.
What I did was to measure the Cgs capacitance with a capacitance meter (1MHz 10mV max) sweeping the Vgs from 0 to Vth and above, leaving the drain connected to the source through a resistor (Vsd=0, Id=0) . Tomorrow I will show my data for a small VMOS form Zetex and a logic-level power MOS IRL530N. I've found that the static gate capacitance measured this way is indeed increases over the threshold region by 2 to 3 times for a very small increase in Vgs.
Apparently this change has a very simple explanation - when the channel of the MOSFET is off, the area of the channel itself under the gate is essentially isolated and Cgs+Cgd consists only from a capacitance between the gate and the metallised source/drain connections. When Vgs reaches the threshold level the channel begins to conduct and the area beneath the gate connects to the circuit, markedly (2 to 5 times) increasing the input capacitance even without the Miller effect - in fact even in the abcence of any drain current! If you put some voltage on the drain it somewhat changes the shape of the curve, but not the character of it.
As you can imagine in an audio amplifier there are many cases where the Miller effect is not really present - i.e. in a common drain follower configuration of the O/P stage. However in a class AB amplifier the Vgs of the output devices goes through the threshold region and that kind of a change in the input capacitance of a MOSFET could be quite significant in understanding of unlinearities in such a stage, especially at high frequencies.
Cheers
Alex
x-pro said:
In the leftmost region of the gate charge plots, the drain current is ramping up in a continuous fashion. The variation of Vgs with time is nearly linear, so it's not like there's a step function of Vgs or anything (bottom graph of figure 5 in AN-944). In this mode, the drain voltage is fixed, Vds is large and the drain current is varying continuously. This is just the mode we are interested in. I would agree that the flat region and beyond is not of interest to us.
But when Vds is constant, Vgd varies when Vgs does. For the IRFP244, Cgs is about 1340 pF. When Vgd is near zero, Cgd is almost as large as Cgs - more than 1200 pF, and varies with Vgd per the datasheet graph. So in your test, variations in Cgd will occur (because Vgd is not constant). These Cgd variations will appear as variations in the measured capacitance between gate and source.
Further, Vgd near zero is not really what we're interested in. Your data is taken with an N-channel gate voltage more positive than the drain. I'd argue that the ramp-up region of the gate charge plot is what we're interested in (fixed and large drain voltage, large Vdg, and continuously variable drain current).
In the ramp-up (leftmost) region of the gate charge plots, the charge is dominated by Cgs. The reciprocal of the slope of the plot at each point in this region is the total input capacitance. If you look at the plot in this region, it's linear. Capacitance variations of 2-3x would appear as slope variations of 2-3x here. But that's not borne out in the data.
andy_c said:
Andy,
most datasheets and application notes only concerned about a switching mode and not really interested in what happens in a linear mode of operation in respect of the input capacitance. Note, that all capacitances curves in datasheets are always taken with Vgc=0 i.e. when the channel is completely isolated!
andy_c said:
As I've said above, the variation of Ciss=Cgs+Cgd is shown for Vgs=0 and has no real meaning for a linear application where the channel is conducting.
andy_c said:
I've taken my data for a small Zetex device both for Vds=0 and Vds=5V, i.e. above the threshold voltage. In a few hours I'll post my experimental graphs and you'll see what it looks like.
andy_c said:
If you look at real graphs of Qg, like the one I attach here from
http://www.fairchildsemi.com/ds/HU/HUF76639P3.pdf
you'll see that these curves are not as nicely looking as most (probably) approximated graphs in other datasheets
. Alex