Hey DIY'ers
I'm shooting in the blind and need some help with the BIAS network.
Do you have any suggestions to implant an 2SA1837 PNP-transistor to this circuit. I want a more stable design.
Best regards
I'm shooting in the blind and need some help with the BIAS network.
Do you have any suggestions to implant an 2SA1837 PNP-transistor to this circuit. I want a more stable design.
Best regards
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At first I did this approach, but hands-on I'm unsure if this really do enough.
I added a PNP and a 1N4148 diode and a 1k resistor
Best regards
I added a PNP and a 1N4148 diode and a 1k resistor
Best regards
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I know.... I can only open the image via the link, if opened in another page.... Sorry, still need to learn this forum 😉
Regards
Regards
The "trick" with this circuit is to make R65 variable and set the ratio of the base resistors of
Q15 to the exact ratio you need. Therefore if you have a driver-output pair giving 4 Vbe's to compensate, the resistor ratio should be 3:1, if you have a 6Vbe triplet then it should be 5:1. By altering R65 you adjust the current in Q15 to give the base voltage needed for the bias. No need for a 1N4148. The PNP can be mounted on the PCB but Q15 on the output/driver heatsink.
The currents (hence value of R65) need to be carefully selected due to the range of Vbe's possible.
I generally use a 220 ohm plust 10k for this adjustment.
High gain transistors are preferable.
Q15 to the exact ratio you need. Therefore if you have a driver-output pair giving 4 Vbe's to compensate, the resistor ratio should be 3:1, if you have a 6Vbe triplet then it should be 5:1. By altering R65 you adjust the current in Q15 to give the base voltage needed for the bias. No need for a 1N4148. The PNP can be mounted on the PCB but Q15 on the output/driver heatsink.
The currents (hence value of R65) need to be carefully selected due to the range of Vbe's possible.
I generally use a 220 ohm plust 10k for this adjustment.
High gain transistors are preferable.
Wow thanks a lot, really helps 🙂
Im doing this PCB (link), and desided to upp the BIAS circuit, but needed some confirmation if this part was done propper... I'll try your suggestions
Shared album - Kåre Nielsen - Google Photos
Best regards
Im doing this PCB (link), and desided to upp the BIAS circuit, but needed some confirmation if this part was done propper... I'll try your suggestions
Shared album - Kåre Nielsen - Google Photos
Best regards
How would you approx estimate the VBE on this one from the looks of the schematic in ratio as mentioned above?
Shared album - Kåre Nielsen - Google Photos
Best regards
hcpower, you have given us about 10% of the info needed to formulate an answer.
To dream up a good BIAS network, you have to consider,
Douglas Self has a whole chapter on this; some of which is good and some suspect. I think Bob Cordell has a better chapter in his latest book
To dream up a good BIAS network, you have to consider,
- the actual output stage: double emitter follower, complementary pairs, different arrangements of triples
- 'emitter' resistors, their sizes & location
- location of the 'bias' sensor: heatsink, on the output devices, on the drivers
- mounting of the 'bias' sensor including any 'thermal insulation'
- size of heatsink
- driver stage
Douglas Self has a whole chapter on this; some of which is good and some suspect. I think Bob Cordell has a better chapter in his latest book
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Your output stage uses triple emitter followers; six Vbe junctions. Your bias network has to provide 6 Vbe voltage drops.
But I can tell you that this type of output stage has TERRIBLE thermal stability.
Let us know what you end up with, do some (real life) tests on thermal stability and let us know.
I will make a guess that a simple Vbe multiplier ( npn + 2 resistors ) will give you as good or better.
I'll let you know when first tests can be performed.
The schematic is very mush inspired by Acurus A250 and it's bigger brother Aragon 8008, so I hope for the best, but.. 😉
Best regards
I'll order a proto PCB with the PNP/NPN bias.... It would be fairly easy to pull out the PNP, and try the simpler NPN without big modifications to the board
Thanks for help 🙂
Kaare Nielsen, DK
Thanks for help 🙂
Kaare Nielsen, DK
The circuit you showed has only 4 Vbe's as far as I can see. There are two pairs of drivers (in parallel) each feeding four output transistors in parallel, so essentially there are just four equivalent junctions to compensate.
The bias circuit I suggested was one I developed specifically for a triplet output stage (pre-driver+driver+parallelled output devices x2) which gave better thermal stability than a single transistor bias.
I mentioned it first some years ago in this forum on another thread somewhere.
For a [driver(pair)+ output (octet)]x2 you may get adequate control from a single bias transistor but it depends on the Vbe of the bias transistor at the current in the VAS stage, but also compared with the current in the driver stage. And the Early effect.
For example if the VAS current is 6mA (usually too low BTW but a popular value) and the bias transistor a BD139, and the driver transistors BD139-BD140 also passing 6mA the Vbe's wont match because the drivers will see a high voltage (30-40V) compared with the bias (2.4V), requiring the Vbe of the bias to be greater. So the "Vbe multiplier" ratio will still end up in the region of 3.5 or so compared with the 4 needed.
The complementary bias arrangement gives you exactly 4Vbe's or any other multiple you need by selecting the resistor ratio and changing the Vbe instead.
The bias circuit I suggested was one I developed specifically for a triplet output stage (pre-driver+driver+parallelled output devices x2) which gave better thermal stability than a single transistor bias.
I mentioned it first some years ago in this forum on another thread somewhere.
For a [driver(pair)+ output (octet)]x2 you may get adequate control from a single bias transistor but it depends on the Vbe of the bias transistor at the current in the VAS stage, but also compared with the current in the driver stage. And the Early effect.
For example if the VAS current is 6mA (usually too low BTW but a popular value) and the bias transistor a BD139, and the driver transistors BD139-BD140 also passing 6mA the Vbe's wont match because the drivers will see a high voltage (30-40V) compared with the bias (2.4V), requiring the Vbe of the bias to be greater. So the "Vbe multiplier" ratio will still end up in the region of 3.5 or so compared with the 4 needed.
The complementary bias arrangement gives you exactly 4Vbe's or any other multiple you need by selecting the resistor ratio and changing the Vbe instead.
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Shared album - Kåre Nielsen - Google Photos
john_ellis is right. Your O/P stage is a double emitter follower .. ie 4 Vbe junctions. MUCH better thermal stability than triple emitter followers. It is also the least sensitive to misset bias current.
My excuse is poor eyesight and your c**p pic 🙂
For this, Nelson Pass's "simple Vbe multiplier ( npn + 2 resistors )" is as good as anything fancier.
MUCH more important is where & how you place the sensing device. See Self's book for details. IIRC, his recommendations for this type of O/P stage are OK
Mea culpa, mea culpa, mea maxima culpa. 😱
john_ellis is right. Your O/P stage is a double emitter follower .. ie 4 Vbe junctions. MUCH better thermal stability than triple emitter followers. It is also the least sensitive to misset bias current.
My excuse is poor eyesight and your c**p pic 🙂
For this, Nelson Pass's "simple Vbe multiplier ( npn + 2 resistors )" is as good as anything fancier.
MUCH more important is where & how you place the sensing device. See Self's book for details. IIRC, his recommendations for this type of O/P stage are OK
I agree. The simple npn+2 resistors (usually 2 + pot in fact) has worked well for all the double emitter follower stages I have built.
The complementary stage was only developed for a triple EF design, but it works well.
It does appear to be slightly better on the double EF but is more complicated.
Positioning the sense transistor is an interesting exercise in itself.
You can calculate the thermal impedance path from the output and drivers to ambient, and as the heatsink temperature will not be as great as the junction of the output device (usually the hottest) you would conclude that you need a greater multiple of Vbe than the 4 I suggested, by the ratio of the thermal impedances.
However if you put the bias right next to an output device (such as on the metal can but insulated) 4Vbe's could over-compensate because the output device(s) is/are hotter than the drivers. (Usually).
Putting the sense device on the same heatsink as the driver and output is a compromise that worked for me in many designs. This may explain why the simple multiplier circuit actually works as well as it does.
The complementary stage was only developed for a triple EF design, but it works well.
It does appear to be slightly better on the double EF but is more complicated.
Positioning the sense transistor is an interesting exercise in itself.
You can calculate the thermal impedance path from the output and drivers to ambient, and as the heatsink temperature will not be as great as the junction of the output device (usually the hottest) you would conclude that you need a greater multiple of Vbe than the 4 I suggested, by the ratio of the thermal impedances.
However if you put the bias right next to an output device (such as on the metal can but insulated) 4Vbe's could over-compensate because the output device(s) is/are hotter than the drivers. (Usually).
Putting the sense device on the same heatsink as the driver and output is a compromise that worked for me in many designs. This may explain why the simple multiplier circuit actually works as well as it does.
A symmetric IPS is going to add to your troubles because it makes the VAS current unpredictable.
The circuit shown in #8 controls the VAS current by resistors on the input differential loads and emitters of the VAS transistors. This configuration more or less has to have these or as you suggest the VAS current could be all over the place.
The downside is that the gain in the VAS stage will be limited and rather less than could be achieved, and the Darlington-like pairs probably add little to the performance, as the resistors I mentioned need to be large enough to control the current.
If the resistor ratios are quite high (and I can't read the component values!!!) then Hawksford's additional resistor in the bias network might be worthwhile in this instance.
The downside is that the gain in the VAS stage will be limited and rather less than could be achieved, and the Darlington-like pairs probably add little to the performance, as the resistors I mentioned need to be large enough to control the current.
If the resistor ratios are quite high (and I can't read the component values!!!) then Hawksford's additional resistor in the bias network might be worthwhile in this instance.