Beast with 1000 JFETs redux?

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#461
Perhaps one could get 80% of the benefit of matching, while expending only 20% of the effort, by simply partitioning the population into four "bins".

Bin_1 is the highest IDSS bin; Bin_2 is the 2nd highest IDSS bin; Bin_4 is the lowest IDSS bin.

Measure each device's IDSS and drop that device into one of the four bins.

Then pick pairs from bins: a valid pair is EITHER (Bin_1 on top, Bin_3 on bottom), OR ELSE (Bin_2 on top, Bin_4 on bottom). JFETS are only approximately matched, rather than precisely matched. With degeneration resistors perhaps this is good enough, while saving lots of time.
 
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#462
The reason for using a different device for the gain position is that the JFET in question has much higher gain than the J113 and therefore will have a lower output impedance and be able to drive a speaker better than a J113. That is the theory. I will be trying different combinations and taking measurements. PCBs for a 10-cell micro beast are on the way to me. The PCBs may be in my hands some time next week.
 
#463
Mark Johnson said:
Perhaps one could get 80% of the benefit of matching, while expending only 20% of the effort, by simply partitioning the population into four "bins".

Bin_1 is the highest IDSS bin; Bin_2 is the 2nd highest IDSS bin; Bin_4 is the lowest IDSS bin.

Measure each device's IDSS and drop that device into one of the four bins.

Then pick pairs from bins: a valid pair is EITHER (Bin_1 on top, Bin_3 on bottom), OR ELSE (Bin_2 on top, Bin_4 on bottom). JFETS are only approximately matched, rather than precisely matched. With degeneration resistors perhaps this is good enough, while saving lots of time.
Click to expand...
Mark, Thank you for your thoughtful suggestion. I truly enjoy reading your posts. Is your suggestion for the complementary buffer or for the single-ended buffer?
 
#464
WT, back in the thread you mentioned you are using resistors to ground at the input and intermediate output positions.

Is this still the case, and what value? Are they both 1k?
woofertester said:
An input resistor to ground has been added. There is a resistor from IntermediateOutput to ground.
Click to expand...

The offset problem turned out to be a input resistor problem. With a 1k input resistor, no more wandering output offset
Click to expand...
 
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#465
Yes. You can see the where these resistors are mounted. I am not 100% certain of the absolute best resistor for these two positions.
I would try 100k at the input and 1k to 10k at the intermediate location.
PCB_02.jpg
 
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#466
After a lot of study of JFET datasheets and some breadboarding, I am thinking of modifying the basic complementary buffer cell to place the source resistors with a trimmer pot. I have seen Mr Pass do this with K170/J74. This would allow balancing buffer cells one at a time while populating the cells.
 
#470
In the attached photo, the DMM on the left is measuring current drawn from the power supply. The range setting is 200 uA. The DMM on the right is measuring Vpinch. The JFET is a J113, Current is 2.4 uA. Vpinch is measured at 2.42 v DC. The DMMs cost $7 / each. The power supply could be a 9-volt battery if you want to be even more el-cheapo.

J113_Vpinch.jpg
 
#471
Here is the same rig measuring a J111. Current draw is 8.2 uA. Vpinch is 8.09v DC. Its nice to have 3 significant digits for the Vpinch measurement using a $7 DMM.

No resistors needed. Just a breadbard, wires, power supply and the DMM.

If you also want to measure Idss, then the second DMM is only another $7.

J111_Vpinch.jpg
 
#472
I thought the point of the 1 ohm was to measure the voltage drop across it and therefore derive the current flow?

I'll quote from the website that I linked - I encourage anyone reading the excerpt below to visit Rod Elliott's site previously linked.

"- Initial Tests
Before you can start working with JFET circuits, you need the values for VGS(off) and IDSS. That's why I included these two tables, because these two parameters are the most critical for any circuit design. They are also the values that require matching, so a simple method for measuring any JFETs that you have (or buy) is fairly important. The test circuit shown below relies on a simple measurement technique, The 1MΩ resistor will cause a small current flow for VGS(off) tests (the meter will show a positive voltage, but it is a negative value). It will be different from the datasheet value, but the 'error' will be tiny and can be ignored. Your multimeter must be able to measure down to millivolts, as the voltage across R1 (1Ω) will show 1mV/mA. If your meter can't measure below 1mV, you will need to increase the value of R1. If you make it 10Ω, the voltage reading is divided by ten to get the current. For example, if you measure 0.012V (12mV), the current is 1.2mA.

Figure 2.1
Figure 2.1 - Test Setup For VGS (off) And IDSS [ 4 ]
'DUT' means 'device under test'. This test is easily performed, needing only an external power supply. Ideally it will have a current limiter so that a shorted device doesn't cause smoke, but if not you can use a 'safety' resistor in series with the supply. You can use up to 100Ω for the safety resistor, and while its inclusion will change your readings, all devices tested will have the same 'error', so the results will balance out. P-Channel JFETs can also be tested, simply by reversing the supply polarity.

When the pushbutton is open, the reading shown on the meter is VGS (off), that voltage where the JFET does not conduct more than a few microamps passed by R2. With the pushbutton pressed, you'll measure IDSS, the maximum current with zero gate voltage. Many JFETs are fully symmetrical, so drain and source can be swapped and you'll get the same readings."
Click to expand...
 
#473
That is for Idss. Idss is milliamps. Vpinch is specified at microamps and sometimes nanoamps. The 1 ohm shunt will create microvolts or nanovolts if you used it for measuring current for Vpinch.

The 1 ohm shunt resistor requires a DMM to measure the voltage across it. Why bother with the shunt when you can use a $7 DMM to meaure current directly?
 
#477
This is an exercise to make the Vpinch current exactly 1uA. The 1 meg resistance of the inexpensive DMM is too large to achieve 1uA. I happen to have a programmable decade resistance PCB that goes up to 10 megohm. It turns out 2.3 megs in parallel with the DMM draws 1 uA.

Vpinch moved 7mV
1uA.jpg
 
#478
Is there utility in testing and matching for Vgs at the desired CCS current rather than Vpinch?

On the other hand does matching for Idss make more sense?

Nelson Pass

Post in thread 'JFET Matching/Sorting'

It has been pointed out elsewhere that for a given part you will see
that the transconductance at a given current is pretty consistent with
Ids, so if you have same type Jfets with different Idss and Vp, you can
still see decent matching for gm at equal current values.

??

Every day is a school day...
yours Beardy (aged 60 and three quarters)
 
#479
Idss is measured at Vgs = 0. For the J113, Idss is measured at Vds = 15 and Vgs = 0.

For the B1 buffer using a current source, Vgs is 0.

For the complementary buffer, Vgs is lower than 0.

My practice is to sort the entire lot of JFET into piles by Idss: 9 mA, 10 mA, 11 mA, etc.

For the complementary JFETs, I sort with the planned source resistor: 33 ohm, 47 ohms, etc

J113_specs.jpg
 
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