Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

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#2,102
iancanada said:
The SCK will be 64*Fs. You can't use input bck, because the input bck if you are running the fifo belongs to a different clock domain.

Ian
Click to expand...

So how must be the connection from the Si570 Clock to the TDA1541A?

As i read in the thread, the guys connected the TDA1541A direct to the FIFO. I think it must be like this:

FIFO------TDA1541A
SCK ---> BCK
WS ----> FS
SD ----> DATA

🙄


Cheers,
Oliver
 
#2,103
dvb-projekt said:
So how must be the connection from the Si570 Clock to the TDA1541A?
Click to expand...

In your case the Si570 is a drop in replacement for the Dual XO board, connections are the same just with the programmable MCLK frequency allowing you some flexibility.

On a separate note I had a glance down the FIFO GB interest list and there is an alarming number of people looking at 2 x Si570. Either a) more people than I expected either have two FIFOs OR b) more people than I expected have missunderstood and think that they need dual Si570 boards for one FIFO. Which is it? I don't know how to work that out.


Cheers,
Chris
 
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#2,104
hochopeper said:
In your case the Si570 is a drop in replacement for the Dual XO board, connections are the same just with the programmable MCLK frequency allowing you some flexibility.
Click to expand...

I understand that, but Ian said that i couldn´t connect the SCK output from the FIFO to the BCK input of the TDA1541A.

That would mean that nobody could use the TDA1541A direct to the FIFO, because of the different clock domain, correct?


:wave:
Oliver
 
#2,105
dvb-projekt said:
I understand that, but Ian said that i couldn´t connect the SCK output from the FIFO to the BCK input of the TDA1541A.

That would mean that nobody could use the TDA1541A direct to the FIFO, because of the different clock domain, correct?


:wave:
Oliver
Click to expand...

I think there was some confusion, same as qusp misunderstood your post that Ian was replying to. The term direct I think they both took to mean direct from your i2s source, before the fifo.

What Ian meant here:

iancanada said:
The SCK will be 64*Fs. You can't use input bck, because the input bck if you are running the fifo belongs to a different clock domain.

Ian
Click to expand...


Is that the 'input bck' is the bck from your source (at the input to the fifo). Ian was stating the obvious that the bck must be the bck from the output of the fifo xo board (single xo or dual xo or si570).


Cheers,
Chris
 
#2,106
dvb-projekt said:
Just for my understanding... If i use this combination:

Input with 192kHz --> FIFO --> Si570 clock --> TDA1541A NOS

what is the SCK output freq. (BCK input)? Could i use it direct, or must i use any logic converter?

Cheers,
Oliver
Click to expand...

dvb-projekt said:
That´s what i mean. The TDA1541A limit for BCK (SCK - FIFO out) is 6.4 MHz.

If FIFO´s SCK = 64*FS than we have:

44.1 KHz --> 2.8224 MHz
48 KHz --> 3.720 MHz
88.2 KHz --> 5.6448 MHz
96 KHz --> 6.144 MHz
176.4 KHz --> 11.2896 MHz
196 KHz --> 12.544 MHz

If this above is correct, i couldn´t use the 176.4 and 196 KHz sampling rates. 🙁
Click to expand...

dvb-projekt said:
So how must be the connection from the Si570 Clock to the TDA1541A?

As i read in the thread, the guys connected the TDA1541A direct to the FIFO. I think it must be like this:

FIFO------TDA1541A
SCK ---> BCK
WS ----> FS
SD ----> DATA

🙄


Cheers,
Oliver
Click to expand...

hochopeper said:
I think there was some confusion, same as qusp misunderstood your post that Ian was replying to. The term direct I think they both took to mean direct from your i2s source, before the fifo.

What Ian meant here:




Is that the 'input bck' is the bck from your source (at the input to the fifo). Ian was stating the obvious that the bck must be the bck from the output of the fifo xo board (single xo or dual xo or si570).


Cheers,
Chris
Click to expand...

We have really some misunderstandings, yes 🙂

Again, this is the connection i would like to do and all my questions above goes to this:


Wave I/O ---------> FIFO ----------> Red Baron DAC

BC ----------------> SCK -----------> BCK
LR ----------------> WS ------------> FS
DT ----------------> SD ------------> DATA

Cheers,
Oliver
 
#2,107
so you would like to make a standard i2s connection?

yes you can do that 😉

the reason why I misunderstood and probably Ian too, is I couldnt think why you would be asking if you could connect BCK to BCK/SCK since on any i2s output, thats what you do.
 
#2,110
Ok, regarding the "time delay" issue we were talking about earlier. I thought of a possible solution (if it does work).
If i run all inputs (which is not sensitive to delay) straight into the FIFO, through a TP OTTO-II, then into the dual XO-board. Then i the source which is sensitive of delay into the secondary input of the OTTO-II (So that it would bypass the FIFO, which where the delay is) This would work, right? if i does - do i need to isolate the i2s signal before going into the dual XO-board?
 
#2,118
But how does the XO-board work then, if it's not only isolated i2s. I know the FIFO buffers the signal and sends to the XO-board, but what difference does the FIFO board have except that it buffers, that makes it impossible to send a isolated i2s into the XO?

I understand that you say it don't work - but my question now is rather why it doesn't work.
 
#2,119
because the clock board is controlled by the fifo main board and its input

its possible you could send it some 48khz audio directly before switching to fool it into staying on 48khz then send it movie data. possible, Ian will have to answer that. but honestly thinking up some mechanical system that may be kludged to work in theory and making something work in reality could easily be very different.
 
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