As you correctly stated, this happens due to the gear method being sometimes innacurate for modelling such unstable oscillations. In such situations it does not necessarily indicate an unstable circuit, but the trapezoidal method should always be used in preference to it.
Theres a very good paper on the subject by kazmierski, nixon, and a few others from southampton university. Should be IEEE.
Peufeu,
Regarding your graphs, what is the rate of change of voltage in your measurement?
I mean, you will not be measuring the effects of Cbcs if you are making static voltage measurements.
Regarding your graphs, what is the rate of change of voltage in your measurement?
I mean, you will not be measuring the effects of Cbcs if you are making static voltage measurements.
Graphs make more sense now. They are current vs time.
What doesn't make sense to me is why the i(cas) and i(norm) are not identical, or atleast much more similar. Are you using the same transistors in both cases?
What doesn't make sense to me is why the i(cas) and i(norm) are not identical, or atleast much more similar. Are you using the same transistors in both cases?
That's because the collector voltage not only makes a leakage current through Cbc, but also modulates the collector impedance (Early voltage)... and possibly other characteristics in the transistor.
Hence a cascoded transistor performs better as a current source (even if the base of the current source is fed from a 0 ohm voltage).
Hence a cascoded transistor performs better as a current source (even if the base of the current source is fed from a 0 ohm voltage).
That's interesting.
I would have expected your transistors to have a Cbc about 5pF or less. When I look at the numbers I don't get this.
Roughly you are swinging the input by 30V and i(norm) is swinging 400uA and i(cas) 140uA.
I'd expect that your transistors have Cbc of the order of 5pF (as should be nromal if slightly large for a VAS stage application). At 10kHz Cbc Z=3Mohms.
30V causing 140uA is a Z=220k.
30V causing 400uA is Z=75k.
In the cascode case I suppose almost all the current change will be through Cbc, emitter current should change very little indeed. 140uA implies ech transistor has Z=430k and C=37pF (min since you would expect the non-linearity to reduce the effective parallel capacitance slightly). Is 37pF about the size of Cbc in your transistors?
In the normal case the impedance of each transistor appears to be 150kohm. With 37pF Cbc this seems rather low because Zce must be of the order of 230k - if capacitive this would be 69pF.
Are these numbers what you would expect?
I would have expected your transistors to have a Cbc about 5pF or less. When I look at the numbers I don't get this.
Roughly you are swinging the input by 30V and i(norm) is swinging 400uA and i(cas) 140uA.
I'd expect that your transistors have Cbc of the order of 5pF (as should be nromal if slightly large for a VAS stage application). At 10kHz Cbc Z=3Mohms.
30V causing 140uA is a Z=220k.
30V causing 400uA is Z=75k.
In the cascode case I suppose almost all the current change will be through Cbc, emitter current should change very little indeed. 140uA implies ech transistor has Z=430k and C=37pF (min since you would expect the non-linearity to reduce the effective parallel capacitance slightly). Is 37pF about the size of Cbc in your transistors?
In the normal case the impedance of each transistor appears to be 150kohm. With 37pF Cbc this seems rather low because Zce must be of the order of 230k - if capacitive this would be 69pF.
Are these numbers what you would expect?
My cascodes :
- NPN BF469 is specified for 1.8pF max capacitance
- PNP BF470 has the same number.
Annoyingly, the Spice model mentions 5 pF for BF469, and 8pF for BF470...
BTW the swing is 60V (30Vpk = 60Vpk-pk)
The Cascoded transistors still look a bit strange to me.
Especially, in simulation I get a large difference (the NPN accounts for most of the non-linearity)...
Maybe it's time to look for another simulator ?
- NPN BF469 is specified for 1.8pF max capacitance
- PNP BF470 has the same number.
Annoyingly, the Spice model mentions 5 pF for BF469, and 8pF for BF470...
BTW the swing is 60V (30Vpk = 60Vpk-pk)
The Cascoded transistors still look a bit strange to me.
Especially, in simulation I get a large difference (the NPN accounts for most of the non-linearity)...
Maybe it's time to look for another simulator ?
60vp-p makes it better. I'd still like to know what your simulator is assuming - 1.8pF is way lower than the sim would suggest.
The "Early" effect is effectively a collector-emitter resistance. If the base current is kept constant the collector current will vary with Vce due to base modulation. In other words beta is Vce sensitive. I'm not familiar with the typical order of magnitude of this resistance - my guess would be >500k and <5M in modern transistors. Perhaps someone has some real figures. I scanned a few datasheets just now but the graphs aren't shown.
In the cascode case Ie is held steady, so changes in beta will cause a change in Ib and Ic (as Ic = Ie-Ib). I would have thought the change in Ib would be vanishingly small.
Could you re-run your sim using a very low f so that the capacitance currents have negligible impact? This would show how much variation is due to non-capacitive effects.
The "Early" effect is effectively a collector-emitter resistance. If the base current is kept constant the collector current will vary with Vce due to base modulation. In other words beta is Vce sensitive. I'm not familiar with the typical order of magnitude of this resistance - my guess would be >500k and <5M in modern transistors. Perhaps someone has some real figures. I scanned a few datasheets just now but the graphs aren't shown.
In the cascode case Ie is held steady, so changes in beta will cause a change in Ib and Ic (as Ic = Ie-Ib). I would have thought the change in Ib would be vanishingly small.
Could you re-run your sim using a very low f so that the capacitance currents have negligible impact? This would show how much variation is due to non-capacitive effects.
I did some simulations for you, taking the problem in reverse. I have built CCS'es, change their collector voltage, and measure the current variations
Thanks again - another very interesting and thought provoking post. I must admit that I'm still thinking about the implications of all this.
Interesting point : the Cbc don't compensate as I said, actually it's the reverse ! The effects add up : when one CCS gives more current, the other draws less.
At first I was quite surprised by how much distortion was present in your current waveforms. Then you mentioned the 30 Volt AC voltage and it made sense. I suppose the best that can be done here is to maximize the output impedance.
Bottom graph is error current going through the ficticious 0 ohm resistor I put at each VAS node (we want this to be 0 ideally).
A zero volt voltage source (say VX) can also be used for this, so that you can use I(VX) for the current. This avoids having to put low-valued (but not zero Ohm!) resistors in the circuit.
A Baxandall Super Pair is even better, but it makes the simulator oscillate. However I don't think these will happen in real life, as the period of oscillations is exactly 4 simulation samples no matter what sample time I use... Therefore I postulate it's an artifact.
When I simulate the super pair within an amplifier, I get an oscillation at a frequency of about 95 MHz that I still haven't been able to kill. One possibility is that your time step is still large enough that you haven't hit the minimum Nyquist sampling frequency to capture the oscillation. If that were the case, what you're seeing may be the effect of aliasing due to undersampling of the oscillation. It just seems like too much of a coincidence that both of us are seeing what looks like oscillation of the super pair. The LTSpice simulator does not use the Berkeley SPICE code base, so we're looking at possible oscillations with two very different simulators. Very suspicious.
(...)Thus I still doubt your circuit could be better than a Super Pair(...)
It looks like the super pair is the best in theory, with the highest output impedance. What bothers me is the oscillation I'm seeing. The Hawksford cascode seems excellent as well, I just don't like its clipping behavior. Of course, never underestimate the "not invented here" human nature aspect 🙂 .
(...)besides something worries me :
How can you be sure the two transistors equally share their base current ? I know, the emitter degeneration resistors play a role...
Are you referring to the Q16/Q19 pair or the Q15/Q22 pair? For Q16/Q19 I'm assuming matched beta, matched Vbe and matched emitter resistors to get matched Ib. For Q15/Q22 the action of feeding the Q22 base current to the emitter of Q15 makes the Q15 and Q22 emitter currents unequal. This is of course a source of error. Assuming matched beta between Q15 and Q22, I get:
IB(Q15)/IB(Q22) = (beta + 2)/(beta + 1)
and
IC(Q15)/IC(Q16) = (beta^2 + 2 * beta)/(beta^2 + 2 * beta + 1)
So the current gain is much closer to one than a normal cascode.
Thanks again - another very interesting and thought provoking post. I must admit that I'm still thinking about the implications of all this.
Interesting point : the Cbc don't compensate as I said, actually it's the reverse ! The effects add up : when one CCS gives more current, the other draws less.
At first I was quite surprised by how much distortion was present in your current waveforms. Then you mentioned the 30 Volt AC voltage and it made sense. I suppose the best that can be done here is to maximize the output impedance.
Bottom graph is error current going through the ficticious 0 ohm resistor I put at each VAS node (we want this to be 0 ideally).
A zero volt voltage source (say VX) can also be used for this, so that you can use I(VX) for the current. This avoids having to put low-valued (but not zero Ohm!) resistors in the circuit.
A Baxandall Super Pair is even better, but it makes the simulator oscillate. However I don't think these will happen in real life, as the period of oscillations is exactly 4 simulation samples no matter what sample time I use... Therefore I postulate it's an artifact.
When I simulate the super pair within an amplifier, I get an oscillation at a frequency of about 95 MHz that I still haven't been able to kill. One possibility is that your time step is still large enough that you haven't hit the minimum Nyquist sampling frequency to capture the oscillation. If that were the case, what you're seeing may be the effect of aliasing due to undersampling of the oscillation. It just seems like too much of a coincidence that both of us are seeing what looks like oscillation of the super pair. The LTSpice simulator does not use the Berkeley SPICE code base, so we're looking at possible oscillations with two very different simulators. Very suspicious.
(...)Thus I still doubt your circuit could be better than a Super Pair(...)
It looks like the super pair is the best in theory, with the highest output impedance. What bothers me is the oscillation I'm seeing. The Hawksford cascode seems excellent as well, I just don't like its clipping behavior. Of course, never underestimate the "not invented here" human nature aspect 🙂 .
(...)besides something worries me :
How can you be sure the two transistors equally share their base current ? I know, the emitter degeneration resistors play a role...
Are you referring to the Q16/Q19 pair or the Q15/Q22 pair? For Q16/Q19 I'm assuming matched beta, matched Vbe and matched emitter resistors to get matched Ib. For Q15/Q22 the action of feeding the Q22 base current to the emitter of Q15 makes the Q15 and Q22 emitter currents unequal. This is of course a source of error. Assuming matched beta between Q15 and Q22, I get:
IB(Q15)/IB(Q22) = (beta + 2)/(beta + 1)
and
IC(Q15)/IC(Q16) = (beta^2 + 2 * beta)/(beta^2 + 2 * beta + 1)
So the current gain is much closer to one than a normal cascode.
traderbam said:
OK, ready for a surprise ? I was surprised !
I put the images there :
http://pfcaillaud.free.fr/elec/vas_sims/
I run sims at 1 Hz, 1k, 10, 100k, 1Meg with fixed ranges so the graphs can be compared (sorry if it gets out of the graph sometimes). So download all the files and use a viewer to cycle between them.
I plotted Ic(t), Ic being the "error" current, and also Ic(Vc), which is interesting.
If we are at low frequencies, capacitances do not act, thus the Ic(Vc) could be a curve (indicating distortion) but it should not look like a circle.
When reactive elements start to act, it starts to look like a circle (sorry for my bad expression, I'm a bit tired here) because, say for Vc=0V, the Ic will be different if you're on the raising or on the falling edge.
My interpretation from the graphics :
At audio frequencies, parasitic caps are not the dominant effect !
Now, all those sims have the bases connected to 0 ohm sources... what would happen with real sources ?
These sims underestimate the importance of the cascode, because in real life, the VAS transistor is fed from a high impedance !
I'm gonna try that right now.
I wont' post more graphics but :
When feeding the VAS transistor from a realistic base impedance of 70k, the un-cascoded case goes boom ! (it distorts like crazy), but all the cascoded cases shift a bit, but don't distort more.
The effect is visible at HF too, there the un-cascoded case is really ugly. The others don't mind the source impedance.
When feeding the VAS transistor from a realistic base impedance of 70k, the un-cascoded case goes boom ! (it distorts like crazy), but all the cascoded cases shift a bit, but don't distort more.
The effect is visible at HF too, there the un-cascoded case is really ugly. The others don't mind the source impedance.
Now, if I step the Cascode's base resistors, their variations in base current will make their emitter voltages move a little, which will in turn influence the sensitive transistors.
Good news is, between a base resistor of 1 Ohm and 100 Ohms, the difference is very small. Super pair is the most insensitive (no change at all), then your circuit (little change), then simple cascode (a bit more).
So bypassing the cascode's bases with low esr caps is not that vital, then.
Traderbam was rightly surprised : it is not the caps which have the most effects below 10 kHz, but the static influence of Vce (early effect and so on).
Food for thought...
Good news is, between a base resistor of 1 Ohm and 100 Ohms, the difference is very small. Super pair is the most insensitive (no change at all), then your circuit (little change), then simple cascode (a bit more).
So bypassing the cascode's bases with low esr caps is not that vital, then.
Traderbam was rightly surprised : it is not the caps which have the most effects below 10 kHz, but the static influence of Vce (early effect and so on).
Food for thought...
btw, my Super pair doesn't oscillate anymore, I've found a way to simulate it right. As the (artifact) oscillations are damped, I just run the simulation twice.
peufeu said:
I tried the technique below to stabilize the super pair and was able to kill the 95 MHz oscillation. 50 Ohms works fine for R9 too, but 25 is just on the hairy edge of oscillation (oscillates on the first cycle of the transient but dies down after that). It also has the good effect of preventing the DC value of the Vcb of Q13 (below) from being zero. Thie gives me the lowest simulated distortion of all the configurations I've tried yet, and doesn't require the device matching of the "funky" circuit 🙂. Clipping is completely clean as well. So I'm switching over to this design.
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peufeu said:
Thanks. I don't think I would have tried any of this stuff without having seen your posts.
Andy,
That looks like a good circuit. Much simpler.
Based on Peufeu's simulator results I'm inclined to think that these circuits are dealing with beta/Vce sensitivity rather than Ccb sensitivity. This is an important finding wrt designing the right compensation. It looks like the one you've got deals with both. I suppose a similar arrangement is needed for the CCS. I also suppose the beta/Vce sensitivity should be a primary criteria when choosing a device for the VAS rather than Ccb.
That looks like a good circuit. Much simpler.
Based on Peufeu's simulator results I'm inclined to think that these circuits are dealing with beta/Vce sensitivity rather than Ccb sensitivity. This is an important finding wrt designing the right compensation. It looks like the one you've got deals with both. I suppose a similar arrangement is needed for the CCS. I also suppose the beta/Vce sensitivity should be a primary criteria when choosing a device for the VAS rather than Ccb.
You mean the device for the VAS Cascode ?
For the VAS itself I think Beta vc Ic is the best parameter.
Can a transistor curve tracer measure these ? Hm. I wish I had an USB curve tracer to send you some curves !
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