Guys,
Think we can agree that perfectly terminated ideal uniform transmission lines look resistive.
Also, we can agree that if series termination is used at the source is used it does work as George has said. (Provided the output device can drive the 100-ohm load okay. At least some CMOS devices can't.)
Also, as Richard said said we do need logic levels at the receiving end.
Most of all the discussion has been academic in the last few posts anyway, but sometimes we have to go through that to understand where each other are coming from.
Reason it seems kind of academic is that what seems to happen in practice with dac boards is:
1. Some series loading may or may not be used, calling it loading in this case rather than terminating since the resistor may be located in the middle of the line and its value is not chosen so as to cut the signals to half-amplitude. The resistor is just used to dampen and flatten out any ringing in the waveform. Waveform amplitude remains at logic levels at the receiver.
2. Traces may run across one PCB, across a short interconnection to another PCB, though some pin header jumpers, along another PCB board trace, up a pin header pin a daughter board, etc. In other words, there is no pretense of a uniform a 50-ohm transmission line.
3. Reason why its done that way is that it works surprising well for the most part, and if signal restoration does turn out to be needed after all that routing around, then reclocking is usual solution.
Think we can agree that perfectly terminated ideal uniform transmission lines look resistive.
Also, we can agree that if series termination is used at the source is used it does work as George has said. (Provided the output device can drive the 100-ohm load okay. At least some CMOS devices can't.)
Also, as Richard said said we do need logic levels at the receiving end.
Most of all the discussion has been academic in the last few posts anyway, but sometimes we have to go through that to understand where each other are coming from.
Reason it seems kind of academic is that what seems to happen in practice with dac boards is:
1. Some series loading may or may not be used, calling it loading in this case rather than terminating since the resistor may be located in the middle of the line and its value is not chosen so as to cut the signals to half-amplitude. The resistor is just used to dampen and flatten out any ringing in the waveform. Waveform amplitude remains at logic levels at the receiver.
2. Traces may run across one PCB, across a short interconnection to another PCB, though some pin header jumpers, along another PCB board trace, up a pin header pin a daughter board, etc. In other words, there is no pretense of a uniform a 50-ohm transmission line.
3. Reason why its done that way is that it works surprising well for the most part, and if signal restoration does turn out to be needed after all that routing around, then reclocking is usual solution.
Last edited:
was thinking 26mhz clock shouldnt be very bothered by few inches of pcb... now i see how wrong that was..
another brain fart here be gentle i am amateur, cant we remove most problems if each part that needs clock has its own clock, and use buffering for data, or else i am not sure how that is done or called, would that be async?
another brain fart here be gentle i am amateur, cant we remove most problems if each part that needs clock has its own clock, and use buffering for data, or else i am not sure how that is done or called, would that be async?
Some decisions need to be made regarding the location and distribution of master clock signals. That would including deciding which clock family master clock is to be active at any given time.
I would suggest to put master clocks very close to the dac chip. One or two dedicated LDO voltage regulators just for clocks should be included. Also needed would be some multi-output low jitter clock buffer chips. Decisions about where the clock buffer outputs will be routed needs to be made.
Also, it needs to be decided what clock frequencies will be used. That depends on what dac sample rates are to be supported, how much increase in jitter will be allowed, and if clock divider(s) and or reclocking options are to be included.
It all kind of starts with the above. Also, if AK4137 ASRC is included, it needs to be decided what inputs are to be routed to it before going to the dac chip, and or if the AK4137 circuitry is to include a bypass option so that AK4137 processing can be skipped if desired.
As is often the case, good design often involves some switching back and forth between top-down and bottom-up design approaches so that eveything can be happily joined together in the middle. (if that makes any sense )
I would suggest to put master clocks very close to the dac chip. One or two dedicated LDO voltage regulators just for clocks should be included. Also needed would be some multi-output low jitter clock buffer chips. Decisions about where the clock buffer outputs will be routed needs to be made.
Also, it needs to be decided what clock frequencies will be used. That depends on what dac sample rates are to be supported, how much increase in jitter will be allowed, and if clock divider(s) and or reclocking options are to be included.
It all kind of starts with the above. Also, if AK4137 ASRC is included, it needs to be decided what inputs are to be routed to it before going to the dac chip, and or if the AK4137 circuitry is to include a bypass option so that AK4137 processing can be skipped if desired.
As is often the case, good design often involves some switching back and forth between top-down and bottom-up design approaches so that eveything can be happily joined together in the middle. (if that makes any sense
)
Last edited:
AK4137 should allow for PCM and DSD inputs. Also, bypass of DSD should be possible, if not both PCM and DSD. It is common for one set of I2S inputs to share both PCM and DSD functions as explained by the following: The three I2S signals are BCLK, LRCK, and DATA. The corresponding DSD signals are DCLK, DATA_R, and DATA_L (in that order). In other words the bit-clock stays the same for both, LRCK becomes the right DSD channel data, and DATA becomes the left DSD channel data. All I2S input pins need corresponding dedicated ground pins that go directly to a solid, continuous ground plane.
The PCM and DSD inputs pins on AK4137 can be tied together in the order described above. There needs to be some means for the control MCU to know whether incoming audio is in PCM or DSD format since AK4137 cannot auto-detect that. If input comes from a USB board, the USB board should have an output pin to indicate if the format is PCM or DSD (the input may need to be be galvanically isolated if such isolation is part of the system design). If the input comes from another device, there needs to be some way to know the format from it or by other means. In some cases a designer has used an MCU to observe the I2C pins to determine what format is being used.
AK4137 also needs an external reference clock input, and one set of external I2C bus inputs (which are to be shared by any I2C devices on the board).
AK4137 should be operated in serial control mode (i.e. via I2C) as much as possible (not pin control mode). Since not all AK4137 functions can be controlled by internal I2C registers, a means should be provided to control remaining functions using pin control via some I2C bus device. A common way of doing that is to use a part such as 74HC595D to control AK4137 pins via I2C bus.
An issue that could potentially cause problems is if devices on other boards designed by other people use duplicate I2C addresses. Most if not all I2C devices allow some means for selecting from a small set of possible I2C addresses. That means should be available to users such as by use of address selection jumpers. For example, on the AK4137 evaluation board dip switches are used to allow selection of I2C addresses.
AK4137 also requires multiple power supply voltages. It is recommended that they be provided by local LDO voltage regulators located on the AK4137 board. The overall system design should include distribution of utility power for digital devices. I would recommend using a 7v or 8v bus for that purpose (rather than 5v, since many regulators have better PSRR with a higher than minimum input/output voltage differential).
Anyone else?
Anything I forgot?
The PCM and DSD inputs pins on AK4137 can be tied together in the order described above. There needs to be some means for the control MCU to know whether incoming audio is in PCM or DSD format since AK4137 cannot auto-detect that. If input comes from a USB board, the USB board should have an output pin to indicate if the format is PCM or DSD (the input may need to be be galvanically isolated if such isolation is part of the system design). If the input comes from another device, there needs to be some way to know the format from it or by other means. In some cases a designer has used an MCU to observe the I2C pins to determine what format is being used.
AK4137 also needs an external reference clock input, and one set of external I2C bus inputs (which are to be shared by any I2C devices on the board).
AK4137 should be operated in serial control mode (i.e. via I2C) as much as possible (not pin control mode). Since not all AK4137 functions can be controlled by internal I2C registers, a means should be provided to control remaining functions using pin control via some I2C bus device. A common way of doing that is to use a part such as 74HC595D to control AK4137 pins via I2C bus.
An issue that could potentially cause problems is if devices on other boards designed by other people use duplicate I2C addresses. Most if not all I2C devices allow some means for selecting from a small set of possible I2C addresses. That means should be available to users such as by use of address selection jumpers. For example, on the AK4137 evaluation board dip switches are used to allow selection of I2C addresses.
AK4137 also requires multiple power supply voltages. It is recommended that they be provided by local LDO voltage regulators located on the AK4137 board. The overall system design should include distribution of utility power for digital devices. I would recommend using a 7v or 8v bus for that purpose (rather than 5v, since many regulators have better PSRR with a higher than minimum input/output voltage differential).
Anyone else?
Anything I forgot?
Last edited:
Schematic is coming along well, hopefully will have the eval board schematics done and posted by tonight, I'm aiming for PCM input at first but would like to see DSD implemented later. Using a shift register seems like a good solution for pin based control over I2C, but I'm thinking I might just go with one of the existing TI chips, like the PCF8574A. Definitely planning on putting LDO's as close to the load as possible, as of right now from an overall system design standpoint, I'm planning on running an 8V bus to each individual subboard, with a capacity of something like 5A on the backplane. I then want to have two seperate regulated 5V buses per board, one lower current, lower noise one for devices that require 5V, and then regulate down further. I'm thinking of using the TPS7A87 regulator for its super low noise specs, does anybody have any better ideas / suggestions / comments.
AK4499 can accept DSD on the PCM input pins. Using the dedicated DSD input pins is not required.
Pin control of AK4499 is not needed at all. Only for AK4137 AFAIK.
A 5-amp, 8v bus is probably overkill for actual current needed. Shouldn't hurt anything though.
PCF8574A would be fine for any needed pin control. Could be used for inputs too, such as perhaps to monitor AK4499 programmable status pin(s).
No objection to TPS7A87. However, probably nothing is needed that is better than what is on the AK4499 eval board. No harm in using a little better if cost is not a issue.
Only area where a little more work might be needed is tuning the Jung regulator to work with larger value electrolytics than are used on the eval board (in order to reduce LF HD). A solution should be okay to mention is that the Jung regulators can be loaded with a resistor from the output to ground. 100mA through the resistor may be plenty to get some audible effect with bigger caps fitted, and not too much load current for pass transistor power dissipation limits.
Pin control of AK4499 is not needed at all. Only for AK4137 AFAIK.
A 5-amp, 8v bus is probably overkill for actual current needed. Shouldn't hurt anything though.
PCF8574A would be fine for any needed pin control. Could be used for inputs too, such as perhaps to monitor AK4499 programmable status pin(s).
No objection to TPS7A87. However, probably nothing is needed that is better than what is on the AK4499 eval board. No harm in using a little better if cost is not a issue.
Only area where a little more work might be needed is tuning the Jung regulator to work with larger value electrolytics than are used on the eval board (in order to reduce LF HD). A solution should be okay to mention is that the Jung regulators can be loaded with a resistor from the output to ground. 100mA through the resistor may be plenty to get some audible effect with bigger caps fitted, and not too much load current for pass transistor power dissipation limits.
Yes, i’m 99% sure you’re right that the Ak4137 is the only one that has registers that can’t be controlled over i2c, but i’ll double check the data sheets tonight. Id like to have a high current bus, to possible integrate an SBC in the same chassis for a full music server, or for any other modules. Planning on throwing it up on github as soon as it’s done, so we can start iterating.
Mark is, of course, a digital and RF expert since he has built a few DACs and read some articles.
Mark is, of course, a digital and RF expert since he has built a few DACs and read some articles.
I think there were some cyclotron and linac RF systems in there somewhere too. Then there were my ham radio days even longer ago, and also the FCC commercial First Class Radiotelephone License (back when there was such a thing)...
Of course, not square waves then.
Last edited:
The analog series of LDO's is also definitely something I would like to explore further, maybe choose to incorporate in this design. The LM723 seems not bad, but I can't find the TI part in anything other than a metal can or military grade from DigiKey/Mouser, and am hesitant to go with the STMicro part. However, with the performance/cost ratio of the TI part and the fact that it performs better than the eval board regs. (I assume, but can't find any listed noise spec for the BA033 series
Last edited:
LM723 DIP and SMD are 'obsolete' status at Digikey. The cans are expensive.
PMIC - Voltage Regulators - Linear | Integrated Circuits (ICs) | DigiKey
PMIC - Voltage Regulators - Linear | Integrated Circuits (ICs) | DigiKey
Don’t use such an obsolete part to save a couple dollars on an expensive design. There are hundreds of alternatives.