Hi to All ! i promise the last rantle but i am just trying to elaborate a little what i have in mind
Let's take the very basic buffer below
will this schematic have intrinsic limits in terms of achievable low THD ?
or an optimal selection of bjts, working conditions, Vsupply could lead to negligible level of THD ?
i have seen proposed very complex and elaborate buffers with 2nd HD down to -130dB at least at sim
Could this schematic provide similar performance with a simpler circuit ?
Thanks a lot again
Let's take the very basic buffer below
will this schematic have intrinsic limits in terms of achievable low THD ?
or an optimal selection of bjts, working conditions, Vsupply could lead to negligible level of THD ?
i have seen proposed very complex and elaborate buffers with 2nd HD down to -130dB at least at sim
Could this schematic provide similar performance with a simpler circuit ?
Thanks a lot again