Mark,
I think I now understand what this meant and why it is so.
I will hard wire all these...
And we can hard wire pin 55 to "H" in order to select I²C (instead of 3-wire serial control interface).
VTSEL (120) can probably be hard wired as well, but I'm not sure to which level. Based on the NZ2520SDA datasheet, I am tempted to say "L".
Last edited:
Digital Pin Analysis Summary
Here is a summary of the digital pin analysis:
Out of 29 pins, 9 can be hard wired. All the others are related to signals or power, which can't go through GPIOs. The only logic pins left are:
113 - PDN: Power-Up, Power-Down
114 - SMUTE: Soft Mute
115 - SCL: Control Data Clock
116 - SDA: Control Data Input
Clearly, SCL and SDA can't be encoded. Therefore, this leaves just two pins (PDN and SMUTE), which are probably best left untouched. Therefore, we probably do not need any I/O expander, and we'll have quite a few pins left on our ERM8 connectors in order to add some more ground return circuits.
Not having to add an I/O expander to our board means that we probably have some room left for some LDOs, but I'm not sure which power supply lines should be on-board regulated in priority. Any suggestions?
Finally, from all the discussions we've had today, I gather that we'll need at least three additional pins:
- CLKS0 and CLKS1: Clock Select 1 and 2, used to select one clock from four possible options.
- MMUTE: Master Mute.
Here is a summary of the digital pin analysis:
Out of 29 pins, 9 can be hard wired. All the others are related to signals or power, which can't go through GPIOs. The only logic pins left are:
113 - PDN: Power-Up, Power-Down
114 - SMUTE: Soft Mute
115 - SCL: Control Data Clock
116 - SDA: Control Data Input
Clearly, SCL and SDA can't be encoded. Therefore, this leaves just two pins (PDN and SMUTE), which are probably best left untouched. Therefore, we probably do not need any I/O expander, and we'll have quite a few pins left on our ERM8 connectors in order to add some more ground return circuits.
Not having to add an I/O expander to our board means that we probably have some room left for some LDOs, but I'm not sure which power supply lines should be on-board regulated in priority. Any suggestions?
Finally, from all the discussions we've had today, I gather that we'll need at least three additional pins:
- CLKS0 and CLKS1: Clock Select 1 and 2, used to select one clock from four possible options.
- MMUTE: Master Mute.
Last edited:
You need to connect PDN, that's the chip's reset pin I think. You may also want to use SMUTE, not sure.
If you prefer to buffer and divide with one device, this Si53301 is a bit overkill but would do the job I think.
https://www.silabs.com/documents/public/data-sheets/si5330x-datasheet.pdf
If you prefer to buffer and divide with one device, this Si53301 is a bit overkill but would do the job I think.
https://www.silabs.com/documents/public/data-sheets/si5330x-datasheet.pdf
Yes, PDN and SMUTE will be connected.
Wow, that's a complex chip! Let me study it first.
On the decoupling cap for the clock, I'm not sure I love either NDK or AKM's solutions. For ceramic caps, generally I prefer the largest capacitance in a given package, assuming the inductance is determined by the package and footprint. NDK's cap is small. AKM has a 0.1, which is better, but adds some random 100 pF caps. My experience is that high Q pF decoupling caps are not a good idea unless you are solving an observed (measured) problem. They are only going to be effective in a very narrow band and the PCB layout / mounted inductance will shift it around quite a bit. When you see round values like 100pF you can almost be sure that the designer pulled that value out of thin air based on some assumptions. Will the clock still work just fine? Yes, I am sure it will, but the decoupling may actually be worse with them on the board because of antiresonance. See Page 18:
https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx
Without doing any measurement, I would probably pick one low inductance cap around 1uF for this. Choose your favorite: reverse geometry LICC (0204, 0306), X2Y, or interdigitated (IDC) cap. Even one regular MLCC is probably fine, or 2 of the same value in parallel. Be aware that the fancy caps are going to make your layout harder (probably) because they require more vias to achieve the low inductance. Not such a big deal for a board using microvias, but with through-hole, 6 holes for an X2Y cap limits what you can do around it on other layers.
https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx
Without doing any measurement, I would probably pick one low inductance cap around 1uF for this. Choose your favorite: reverse geometry LICC (0204, 0306), X2Y, or interdigitated (IDC) cap. Even one regular MLCC is probably fine, or 2 of the same value in parallel. Be aware that the fancy caps are going to make your layout harder (probably) because they require more vias to achieve the low inductance. Not such a big deal for a board using microvias, but with through-hole, 6 holes for an X2Y cap limits what you can do around it on other layers.
Last edited:
Normally, the reason a DAC and ADC might need to be on the same clock is so that one can playback and record at the same time without resampling to keep them in sync. Its common in recording situations to need to be able to listen to a partially complete recording while overdubbing a new track. However, resampling might be an okay option. There is an AK4137 on the AK4499 eval board which can be used for exactly that. Otherwise, usually the ADC should define the master clock for the system.
Last edited:
Maybe a little too much additive jitter for audio. They only show phase noise graphs down to 100Hz, but we are interested in that down to 1Hz. Humans are especially sensitive to dac jitter effects between 10Hz and 1Hz.
So you say, with no evidence of this oft repeated close-in phase noise bogeyman.
I don’t know if you read the datasheet closely, though. If the close-in phase noise is what you care about, you can see in the graph that the close in phase noise of this part is better than the clock they tested with based on the convergence at 100 Hz. The level shown at 100 Hz is comparable to the On Semi clock buffer. This part, and the On Semi part are overkill for any (baseband) data converter application, period.
With a dedicated clock supply you are probably better off with the simpler solution of the 1:4 buffer and D-FF divider, but it’s academic.
Last edited:
True enough, from your perspective and the perspective of others similarly disposed. Moreover, this case is only one example of where we tend to disagree. Not everything people can hear has been thoroughly researched as of yet, IMHO. In addition, much of the prior psychoacoustic research is very questionable. As DPH and I have both mentioned, Ioannidis is at the forefront of pointing out some of the problems:
John Ioannidis - Wikipedia
http://robotics.cs.tamu.edu/RSS2015NegativeResults/pmed.0020124.pdf
Thus, I must go by own ears and own experience when it comes to some things. Working with Jam has been a real eye-opener, or perhaps I should say an ear-opener. Very interesting work he does, but virtually all of it will remain unpublished as is the case with most other recent audio and psychoacoustic research. It is all proprietary, not publicly funded. Very unfortunate, but that's the way it is.
AK4490/4493/4497/4499 - works fine with 512fs Mclk (22/24) with PCM 44.1-768kHz in Auto Setting Mode.
Don't know about fine. AK4499 seems to work with 45/49 sometimes in DSD modes too. However, when it works other than as described in the data sheet it sounds different. Interesting difference in sound, but haven't figured out how to make it work reliably in DSD mode when double-clocked. Best to stick the data sheet I think.
Did not try it with DSD512, but for DSD64-256 there is no problem with 22/24 Mclk for all 449x.
I think I understand that part now. Does it mean that we should still provide a way to get the clock from outside of the DAC board? If so, should we rely on the ERFM8 connector, or should we use a separate Hirose U.FL PCB-mount socket? Or should we go for a more reliable PCB-mount socket? If so, which one would you recommend that would remain small?
Many options here. Everything you're writing makes sense to me, but I'm left wondering what the best course of action should be. It won't change the design of the PCB that much, so we can easily change our mind later, but we should decide what we get started with.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.