Just remembered that although my USB board, the JLsounds one, uses 45/49Mhz clocks, for most PCM sample rates and for all DSD, AK4499 needs clocks half that frequency (which are also available in NDK SDA). AK4499 only uses the higher frequency clocks for 768kHz and whatever the other one is up around there.
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I was surprised by these numbers as well, but did some more research before pushing back
22.5792MHz and 24.5760Mhz are what we need, right?
At a minimum. If you want 768kHz PCM then you need more clocks or some other thing like a low-jitter clock divider.
Right. If I understand things correctly, it looks like I would need 36.8640MHz and 49.1520MHz.
My bad! Looked at the tables the wrong way. 45.1584MHz and 49.1520MHz.
And I guess I would need two pins and some gates to select the right clock. Time to pay a visit to the SN74 family...
2-to-4 Line Decoder
If we go with 4 clocks, we will need a 2-to-4 line decoder. Unfortunately, the only one I could find is the SN74LVC1G139, but it would require to be mounted upstream of an inverter, because the clocks expect a high signal to be turned on, while the SN74LVC1G139 returns three high signals and a low one, instead of three lows signals and one high signal that we need. There are other 2-to-4 line decoders that would provide the right kind of signal, but they usually come in dual-channel packages. Any idea where I could find a single-channel version?
If we go with 4 clocks, we will need a 2-to-4 line decoder. Unfortunately, the only one I could find is the SN74LVC1G139, but it would require to be mounted upstream of an inverter, because the clocks expect a high signal to be turned on, while the SN74LVC1G139 returns three high signals and a low one, instead of three lows signals and one high signal that we need. There are other 2-to-4 line decoders that would provide the right kind of signal, but they usually come in dual-channel packages. Any idea where I could find a single-channel version?
You could use an I2C shift register chip and run it using the same I2C bus as for the dac chip, just give it a different address. Clock selection in that case would come from the MCU. It would need sample rate and clock family info from the USB board. Also, depending on the ultimate USB board, it might always use 45/49 clocks regardless of what the dac needs, or it might always use 22/24. Depends. In either such case a different clock scheme would be needed.
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Thanks Terry for the comments
Got around to reading the datasheet this morning and it all falls into place.
Including the caveat to only use voltage summing by AKM.
With only a 6db (not insignificant) decrease in the noise floor, one wonders if it will be a significant audio consideration. Time will tell. If it was on the front end, I'm all for any and all things that lower the input noise.
Cheers
Alan
Got around to reading the datasheet this morning and it all falls into place.
Including the caveat to only use voltage summing by AKM.
With only a 6db (not insignificant) decrease in the noise floor, one wonders if it will be a significant audio consideration. Time will tell. If it was on the front end, I'm all for any and all things that lower the input noise.
Cheers
Alan
Well, I'm only planning to design a single USB board: the one with the STM32H743 MCU. If someone wants to use a different USB board, they'll have to use whatever we use for the interconnect. I am not planning to make the DAC board totally agnostic from the USB interface it would be used in conjunction with.
The MCU is the USB board.
TCA9555 I²C I/O Expander
Mark's suggestions to use the same I²C bus as the one used by the DAC chip is a good one. With that in mind and the fact that we might need some additional I/Os, I think we should use a TCA9555 I²C I/O Expander to drive the clock selection and these 10 pins on the DAC chip:
- PSN
- LDOE
- PDN
- SMUTE/CSN
- DIF0/DZFL
- DIF1/DZFR
- VTSEL
- TEST
That way, we save 8 pins on our ERM8 connectors and we can better isolate our critical digital circuits.
Using ERM8 connectors with more positions (more circuits) is not an option because the shielded version is only available for up to 30 positions (60 circuits), which is the model that we are using already.
And like Mark mentioned earlier, CAD0 and CAD1 must be hardwired.
I suggest 00 as address for the DAC chip, and 111 for the I/O expander.
Mark's suggestions to use the same I²C bus as the one used by the DAC chip is a good one. With that in mind and the fact that we might need some additional I/Os, I think we should use a TCA9555 I²C I/O Expander to drive the clock selection and these 10 pins on the DAC chip:
- PSN
- LDOE
- PDN
- SMUTE/CSN
- DIF0/DZFL
- DIF1/DZFR
- VTSEL
- TEST
That way, we save 8 pins on our ERM8 connectors and we can better isolate our critical digital circuits.
Using ERM8 connectors with more positions (more circuits) is not an option because the shielded version is only available for up to 30 positions (60 circuits), which is the model that we are using already.
And like Mark mentioned earlier, CAD0 and CAD1 must be hardwired.
I suggest 00 as address for the DAC chip, and 111 for the I/O expander.
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Maybe its time to start on that? You know, top down and bottom up at the same time.
By the way, have you ordered a USB board for your eval board yet? I2SoverUSB - I2S over USB Audio
Also, to get started I would suggest an Arduino like I use, which also happens to require an FTDI board:
https://www.amazon.com/Adafruit-Pro...inket+pro+3.3&qid=1567290301&s=gateway&sr=8-1
https://www.amazon.com/TinySine-Mic...eywords=ftdi&qid=1567290329&s=gateway&sr=8-17
Almost. I need to get the headphone and headphone preamp first.
BUt I'll get all these kits immediately after.
Most of this was already mentioned by Mark, but you'll need 2 clocks of course.
I don't know if you want to put them on the DAC board, because you have ADCs as well. It depends on how the USB receiver works, but I don't know if you can run the I2S input at a different rate (or even the same rate but not frequency or phase locked) than the I2S output if the device is being used in master mode.
As for the resistor, it's a crude form of termination / impedance matching that's frequently used for single ended CMOS logic. It's not always necessary, and the value can vary depending on the output Z of the driver. I would probably start with 33 ohms. Measuring isn't going to be that helpful unless you know how well your setup works. You would want a faster scope, but more importantly, an appropriate probe. A standard Hi-Z 10:1 scope probe has too much input capacitance and will load the output. A very low capacitance active probe would be better. I have used probes in this series for LVDS:
N2752A InfiniiMode 6 GHz Active Differential Probe | Keysight (formerly Agilent’s Electronic Measurement)
https://www.keysight.com/upload/cmc_upload/All/Probing-6-Hints-Scopes-Dec12-2007-webcast.pdf
I've never tried a passive low Z transmission line probe, but those might also work and are much cheaper. You can DIY one, too.
In reality, I would just put something from 0-50 ohms down and call it a day.
As far as distribution, the critical path is to the DAC and ADC chips. Sending it back to the USB receiver or other ICs can be done with whatever buffer you find convenient, it doesn't necessarily have to have fs additive jitter. The buffer Mark suggested is good. It's only critical if you prefer not to have a fan-out of 2 on the initial connection and want to feed the DAC / ADC from the buffer as well. I have not tried this, but you could potentially use even larger value series resistors at the buffer's output for the non-critical clock paths like back to the USB receiver in an attempt to lower the slew rate for EMI purposes.
To divide by 2 before the DAC, I would use a TinyLogic UHS or 74LVC series D-FF like NC7SZ74.
The LT3042 is a little bit better than ADM7150, but there is no problem using ADM7150.
Chris,
Thanks a lot for this. A lot to chew on.
The ADC will be a totally separate system, so I think we can ignore it for now.
If the LT3042 can do the job, I'd rather use it, because we'll use it for the PSU board as well, and the fewer different parts we have to use, the better.
Digital Pins Analysis
This sheet outlines the functions of all the digital pins on the AK4499EQ, organized by mode. This is helping me understand what should be done with these pins.
One thing that I do not understand is why the DSD pins are duplicated (43..47 and 50..54).
What is clear is that we want to support both PCM and DSD, therefore we must be in Register Mode.
This sheet outlines the functions of all the digital pins on the AK4499EQ, organized by mode. This is helping me understand what should be done with these pins.
One thing that I do not understand is why the DSD pins are duplicated (43..47 and 50..54).
What is clear is that we want to support both PCM and DSD, therefore we must be in Register Mode.
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