It more depends on the number of vias and their placement relative to the pads of the cap and the device. Your point stands, though.
Don't know. Allo found they needed 10 for their new ES9038Q2M compact USB dac. AKM got away with only 4 for the more widely spaced eval board. Ott says it takes about 12 to meet all the goals laid out for board optimization. Gets expensive though. Nobody said its easy to design well at -120dB and lower.
I think you've just answered my question: 10 is the minimum, and we might want to go to 12. AKM gets away with it because their reference design is made of two huge boards. We're trying to condense all that into a single tiny board. There is no way that we could do that with 4 layers if experienced designers can't do it with 10...
I'll start with 10.
Our board has a lot of expensive components anyway, so the layering won't change the BoM that much.
It's hard to say from first glance, but I think your layout is too density constrained to work well here. You don't even have room for vias near the caps that I can see in some places. I'm not sure how hard and fast your board dimensional requirements are, but I'd relax that if you can and place things where they are functionally as optimal as possible first.
I can't guarantee this would compromise performance even if you do manage to route it with a lot of layers, but it might depending on how things shake out.
Is there a reason you aren't using the bottom layer of the PCB for components? The way to easily route designs that must use every square millimeter of space seems to be to use both sides for components and also use blind / buried vias, microvias, and/or via-in-pad.
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I get that. This first layout was done to establish a density ceiling. We'll take it down from there.
Stupid question: can vias be placed within soldering pads? This EE thread offers some useful answers, but I'd love to get your take on it.
Generally it's a bad idea unless you are paying for them to be filled with conductive epoxy or similar and capped. They will wick solder otherwise and cause voids. Tenting the bottom with solder mask is unreliable to prevent this.
Understood. But if I pay for it, is there any downside? The board's BoM is around $200, so I don't think it will make that much of a difference from a cost standpoint.
I don't think there is a downside in that case necessarily, but it's usually cost prohibitive for small runs, don't know what your prototyping budget looks like.
Via-In-Pad Guidelines: How to Choose the Best Routing for Your SMDs | Tempo
Screaming Circuits: Via in Pad
Edit: another reference
https://www.4pcb.com/TechTalk_Highly_Reliable_Via_In_Pad_Design_February_2013.pdf
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And I'm with Mark that ultra-dense analog routing may cause some unwitted problems, both from capacitive and, more importantly, inductive coupling and crosstalk.
If you don't fully identify, seperate and minimize all of your current loops in an intermediate, geometry-centric "pre-routing" schematic you'll be facing problems. One wrong connection of a bypass cap can ruin it all (hint: never connect the opamp rail bypass caps individually to a GND plane that doubles up as a reference plane, rather connect their GND pads directly on the top layer and then via to the plane right under the chip. This is even recommended when you have separate power and reference GND planes because the planes speak to each other, notably when they are in adjacent layers on the same side of the PCB core, with little distance between them).
Rather than crowing one single side of the PCB to the max, I'd use both outside layers for components to reduce total board space. And be generous when it comes to the number of layers.
If you don't fully identify, seperate and minimize all of your current loops in an intermediate, geometry-centric "pre-routing" schematic you'll be facing problems. One wrong connection of a bypass cap can ruin it all (hint: never connect the opamp rail bypass caps individually to a GND plane that doubles up as a reference plane, rather connect their GND pads directly on the top layer and then via to the plane right under the chip. This is even recommended when you have separate power and reference GND planes because the planes speak to each other, notably when they are in adjacent layers on the same side of the PCB core, with little distance between them).
Rather than crowing one single side of the PCB to the max, I'd use both outside layers for components to reduce total board space. And be generous when it comes to the number of layers.
Thanks a lot for the links, much appreciated. I think I will try to avoid them.
KSTR,
Thank you so much for this. I think you are right: now that I know that everything will fit, I should spread components out across both layers. I'll follow AKM's lead by keeping the transistors on the back side, but I'll also put more small capacitors and resistors there.
I will also try to move the L1, R1, L2, and R2 regulator circuits closer to where they are needed, probably putting their ICs and small decoupling capacitors on the underside, leaving only the large capacitors on the top side.
And I will start the design with ten layers, but I won't use any pad vias. This will keep the manufacturing process simpler and faster. I'm not too worried about manufacturing costs, but I am concerned about manufacturing lead teams, especially during the prototyping phase.
It boggles my brain that you still think I'm saying that the LRCK is used to clock the multi-bit converter. I am not and never have I said so. What Mark said is exactly what I am talking about in one way or another, but he got it and you didn't seem to.
I shall make an analogy for what I am trying to explain.
Some of the SigmaDSP chips from AD run at an internal clock speed of around 400MHz. They work with a conversion start pulse that is derived directly from the LR clock.
Data is clocked into the input registers and on the completion of the word, dictated by the LR clock, a start pulse is initiated, the data is passed into the DSP core, processed (at 400MHz), and then placed into the output buffer. For a given DSP program is takes X amount of time for the data to be placed into the output buffer.
Carrying this analogy over to the DS DAC I am saying that a data word is clocked into the input register/buffer. The word is complete upon a transition on the LR clock. Upon this transition it triggers the conversion process whereby the data word is passed from the input buffer to the rest of the converter, clocked by the master clock. The conversion process has an inherent group delay after which an analogue voltage is developed on the output of the DAC for that sample.
Then each new word has its conversion triggered by the LR clock. So jitter on the LR clock would displace the samples in time from where they really should be and the resultant analogue waveform would be imperfectly reproduced on the output.
This is all I am saying how I thought the situation was.
I thought that the entire point of an ASRC was to remove the jitter present in the data stream and recreate it anew clocked (via division) to a new low jitter master clock. That jitter on the master clock and the data lines were important.
If you're saying that that isn't the case then this is a big change in how I had been lead to believe that things worked.
I am generally confused as to how you think this all works. Mark doesn't agree with you either, unless I am misunderstanding him. Not that it matters, because this isn't a matter of opinion. Go ask AKM or something. This discussion is getting old fast.
No, no, no... conversion is not triggered by LR clock. It is triggered by MCLK. It is not even possible for it to have been triggered by LR clock when the converter rate is much higher than this.
I think you have a large misunderstanding somewhere, maybe in how digital works. How could jitter on the DATA signal do anything? It is sampled (latched) when the edges of the clocks occur. It is NOT "jitter" if you violate setup and hold timing or the output is metastable, it's a broken system.
I don't know how to put this any more simply.
No, no, no... conversion is not triggered by LR clock. It is triggered by MCLK. It is not even possible for it to have been triggered by LR clock when the converter rate is much higher than this.
I think you have a large misunderstanding somewhere, maybe in how digital works. How could jitter on the DATA signal do anything? It is sampled (latched) when the edges of the clocks occur. It is NOT "jitter" if you violate setup and hold timing or the output is metastable, it's a broken system.
I don't know how to put this any more simply.
@ishizeno
I was looking at your XMOS board mockups a few pages back and I was wandering what you were planning to do for power.
These XMOS devices' cores run at 1V and are pretty power hungry.
For example my XUF208 design draws about 250mA @ 1V and it's only 8-core.
I haven't seen the 32-core parts' datasheets but I'm pretty sure that their power consumption will be close to 4 times that of my chip's.
Getting 1V at 1A is no problem if you use a switching dc-dc PS but sound-wise it's considered a no-no.
If you use an LDO you'll need to sink several watts of power. I'm pretty sure your design's thermal capacity can't handle that, combined with the XMOS' own requirements.
Other than that, my general advice is this: If you're indeed going for SQ, begin by laying out the boards according to PCB design best practices. That and only that will determine your boards' footprints. You'll see that for no-compromise (or at least close to no compromise) designs you'll need a lot more space than what you've budgeted.
I was looking at your XMOS board mockups a few pages back and I was wandering what you were planning to do for power.
These XMOS devices' cores run at 1V and are pretty power hungry.
For example my XUF208 design draws about 250mA @ 1V and it's only 8-core.
I haven't seen the 32-core parts' datasheets but I'm pretty sure that their power consumption will be close to 4 times that of my chip's.
Getting 1V at 1A is no problem if you use a switching dc-dc PS but sound-wise it's considered a no-no.
If you use an LDO you'll need to sink several watts of power. I'm pretty sure your design's thermal capacity can't handle that, combined with the XMOS' own requirements.
Other than that, my general advice is this: If you're indeed going for SQ, begin by laying out the boards according to PCB design best practices. That and only that will determine your boards' footprints. You'll see that for no-compromise (or at least close to no compromise) designs you'll need a lot more space than what you've budgeted.
It's your opinion that a switching regulator is a no-no. I disagree, and I think it's the only sane thing to do for processors and digital ICs that use a lot of current at a low core voltage. For lower current ones like this, you can at least use a buck regulator to bring it down to within around 0.5V of the required voltage and use a linear regulator to help clean it up.
I agree with your comments on the layout in general though.
The CM6631A and CM6632A seem to use much less power than the XMOS chips and may be worth looking at, but they have different limitations.
I agree with your comments on the layout in general though.
The CM6631A and CM6632A seem to use much less power than the XMOS chips and may be worth looking at, but they have different limitations.
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I have yet to work on the power supply for the USB board (aka XMOS board).
As far as PCB layout is concerned, I agree with you: I first need to learn the best practices there. But I have good hope that I can make it fit within the 35mm × 35mm that we have to play with (for the USB board).
For the DAC board (the one with the AK4499EQ on it), it will certainly be a challenge, but this is what makes the project interesting.
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