raitraak said:
thanks 😉
hi raitrack,
i would suggest that you add a series resistor on the collectors of Q63 and Q72, say 10K, 2 watt, and you can forgo the heatsinks HB1 and HB2...😀
i would suggest that you add a series resistor on the collectors of Q63 and Q72, say 10K, 2 watt, and you can forgo the heatsinks HB1 and HB2...😀
Hey!
It seems that I have no time to put into this project, so the progress will be slow.
When I was examining the circuit and noticed something odd. Going back to the original schematics from Slone, the "error" was there too. Lets describe, but first the schematics from Slone's book:
Scematics
First finding the input diff pair current:
current = ((voltage drop on two diodes D4,D5) - (voltage drop on Q6))/R11 = (1.4 - 0.7)/390 = 1.8mA
Current will be shared equally between two legs (Q1 and Q2). So on the collector of Q1 there should be voltage of 55 - 0.9mA * 6.8kohm = 48.9V
The same voltage is at VAS. BUT cascode transistor for VAS has base voltage of 55 - 3.9 = 51.1 volts. So the cascode transistor Q8 is reverse biased.
It seems that the circuit will not work... Am I correct?
Regards,
Aq
It seems that I have no time to put into this project, so the progress will be slow.
When I was examining the circuit and noticed something odd. Going back to the original schematics from Slone, the "error" was there too. Lets describe, but first the schematics from Slone's book:
Scematics
First finding the input diff pair current:
current = ((voltage drop on two diodes D4,D5) - (voltage drop on Q6))/R11 = (1.4 - 0.7)/390 = 1.8mA
Current will be shared equally between two legs (Q1 and Q2). So on the collector of Q1 there should be voltage of 55 - 0.9mA * 6.8kohm = 48.9V
The same voltage is at VAS. BUT cascode transistor for VAS has base voltage of 55 - 3.9 = 51.1 volts. So the cascode transistor Q8 is reverse biased.
It seems that the circuit will not work... Am I correct?
Regards,
Aq
No,raitraak said:
First finding the input diff pair current:
current = ((voltage drop on two diodes D4,D5) - (voltage drop on Q6))/R11 = (1.4 - 0.7)/390 = 1.8mA
Current will be shared equally between two legs (Q1 and Q2). So on the collector of Q1 there should be voltage of 55 - 0.9mA * 6.8kohm = 48.9V
the VAS forces the LTP to operate unbalanced.
=Bad Design.
AndrewT said:
No,
the VAS forces the LTP to operate unbalanced.
=Bad Design.
Does increasing the cascode voltage reference zeners (D3 and D6) say to 10 volts help the design? Of course this limits the VAS voltage range. Or is it better to lower the value of LTP collector resistors (R1, R2, R6, R7)?
OR can You suggest some other schematic, that overperforms this one?
Regards,
Aq
The same voltage is at VAS. BUT cascode transistor for VAS has base voltage of 55 - 3.9 = 51.1 volts. So the cascode transistor Q8 is reverse biased.
hmmm...between bases of Q7 and Q8, there will be 2.2volts, more than enough for it to operate...
Q7 supplies current to Q8 so for as long as its colletor is reverse biased, it will work happily...😀
Tony said:
hmmm...between bases of Q7 and Q8, there will be 2.2volts, more than enough for it to operate...
Q7 supplies current to Q8 so for as long as its colletor is reverse biased, it will work happily...😀
Hey!
The voltage between bases is wrong polarity, so no conduction in "supposed" quiescent condition. After pushing LTP to inbalance, voltage on Q7 base will be higher than of Q8 and vas will conduct current of 15 mA instead of 35mA.
Aq
Take a first guess at VAS bias current.
10mA gives Vr14=1500mV
VbeQ7~=600mV
Therefore Vr1=600+1500=2100mV.
Ir1=2100/6800=0.31mA.
Ir2=1.8-0.31=1.49mA
Ratio of Ir1:Ir2=1:4.83, unbalanced.
Try for Ir14=5mA, 15mA and 20mA to see the pattern developing.
I suggest you make R8 and R11 adjustable and remove P1 replace with 2off 100r.
Then reduce R1, 2, 6 & 7 to around 1k0.
Better still select a properly designed schematic.
10mA gives Vr14=1500mV
VbeQ7~=600mV
Therefore Vr1=600+1500=2100mV.
Ir1=2100/6800=0.31mA.
Ir2=1.8-0.31=1.49mA
Ratio of Ir1:Ir2=1:4.83, unbalanced.
Try for Ir14=5mA, 15mA and 20mA to see the pattern developing.
I suggest you make R8 and R11 adjustable and remove P1 replace with 2off 100r.
Then reduce R1, 2, 6 & 7 to around 1k0.
Better still select a properly designed schematic.
Hey!
To be honest, I am running out of schematics to use, I could drop mirror topology and use something like the following, but is it as good as mirrored one?
Slone's Design
I have also tried to understand Lynx16 and Lynx14 schematics, but they are too complicated and need too expensive parts.
Lynx's Designs
Could anybody recommend something with mirrored input? Or something as good?:=)
Regards,
Aq
To be honest, I am running out of schematics to use, I could drop mirror topology and use something like the following, but is it as good as mirrored one?
Slone's Design
I have also tried to understand Lynx16 and Lynx14 schematics, but they are too complicated and need too expensive parts.
Lynx's Designs
Could anybody recommend something with mirrored input? Or something as good?:=)
Regards,
Aq
Hey!
I have dropped the mirror topology and redrawn the schematics. Hope I didn't make any mistakes. When I'll find some time I'll draw the layout too. It's time to finish this project already!🙂
Main Schematics
Aq
I have dropped the mirror topology and redrawn the schematics. Hope I didn't make any mistakes. When I'll find some time I'll draw the layout too. It's time to finish this project already!🙂
Main Schematics
Aq
Hi,
it looks like the output stage is biased to 300mA (20mV across 0r33).
This will bias the drivers to ~2.6A and the pre-drivers to ~12mA.
Is that what you intended?
Add an RC filter just before the base of the protection transistors (Q28 & Q29). This will allow you to tune the transient peak current that can pass without triggering the protection (makes it sound better). The protection circuit shown will limit both DC output and ACpeak output to the same values, but the transistors can withstand far more peak dissipation on transients, sometimes as much as 100Times)
R24 is liable to trigger the VAS protection too early. It will start to turn on Q13 at ~20mA. The VAS passes ~14mA at quiescent state and your 20mA limiter will only allow modulation of the VAS current to -13mA + 6mA. (1mA to 20mA peak to peak swing).
I think R24 should be reduced to 10r to allow 40mA to pass before triggering the protection. This is ~ three times the VAS bias.
Other than these minor value adjustments, it looks good.
Try adding pads/traces for extra compensation components that may be required during debugging.
Benson's XLS predicts 350W into 8ohm 60degree phase angle as continuous within the 90degC DC SOAR.
650W into 4ohm 60degree phase angle just outside the DC 50degC SOAR.
This is a mighty amplifier. Build the PSU to match. This could be a genuine 600 to 650W amplifier for a 4ohm speaker. It deserves ~1000VA and +-45mF of smoothing per channel.
it looks like the output stage is biased to 300mA (20mV across 0r33).
This will bias the drivers to ~2.6A and the pre-drivers to ~12mA.
Is that what you intended?
Add an RC filter just before the base of the protection transistors (Q28 & Q29). This will allow you to tune the transient peak current that can pass without triggering the protection (makes it sound better). The protection circuit shown will limit both DC output and ACpeak output to the same values, but the transistors can withstand far more peak dissipation on transients, sometimes as much as 100Times)
R24 is liable to trigger the VAS protection too early. It will start to turn on Q13 at ~20mA. The VAS passes ~14mA at quiescent state and your 20mA limiter will only allow modulation of the VAS current to -13mA + 6mA. (1mA to 20mA peak to peak swing).
I think R24 should be reduced to 10r to allow 40mA to pass before triggering the protection. This is ~ three times the VAS bias.
Other than these minor value adjustments, it looks good.
Try adding pads/traces for extra compensation components that may be required during debugging.
Benson's XLS predicts 350W into 8ohm 60degree phase angle as continuous within the 90degC DC SOAR.
650W into 4ohm 60degree phase angle just outside the DC 50degC SOAR.
This is a mighty amplifier. Build the PSU to match. This could be a genuine 600 to 650W amplifier for a 4ohm speaker. It deserves ~1000VA and +-45mF of smoothing per channel.
Hey!
Thank you AndrewT for valuable feedback!!!
Can You explain the number 2.6 A for drivers? Both my calculation (~1.6V/47ohm) and simulation show that drivers are running on 34mA. Predrivers are intended to work ~14mA. Should I increase these values?
Added filter with T = 0.1 s (R = 470ohm and C = 220uF).
Done.
I will use a 800VA transformer. I planned using +-20mF, so I'll need to increase it. 40mF should be suitable?
Updated Schematics
Aq
Thank you AndrewT for valuable feedback!!!
it looks like the output stage is biased to 300mA (20mV across 0r33). This will bias the drivers to ~2.6A and the pre-drivers to ~12mA. Is that what you intended?
Can You explain the number 2.6 A for drivers? Both my calculation (~1.6V/47ohm) and simulation show that drivers are running on 34mA. Predrivers are intended to work ~14mA. Should I increase these values?
Add an RC filter just before the base of the protection transistors (Q28 & Q29). This will allow you to tune the transient peak current that can pass without triggering the protection (makes it sound better). The protection circuit shown will limit both DC output and ACpeak output to the same values, but the transistors can withstand far more peak dissipation on transients, sometimes as much as 100Times)
Added filter with T = 0.1 s (R = 470ohm and C = 220uF).
I think R24 should be reduced to 10r to allow 40mA to pass before triggering the protection.
Done.
It deserves ~1000VA and +-45mF of smoothing per channel.
I will use a 800VA transformer. I planned using +-20mF, so I'll need to increase it. 40mF should be suitable?
Updated Schematics
Aq
I misread the 47r as 0.47
14 & 34mA seems a bit low. Look at the gain Vs Ic graphs and also the fT vs Ic graphs.
220uF sounds to big.
220nF or maybe as high as 1uF. Try a low value to be safe.
14 & 34mA seems a bit low. Look at the gain Vs Ic graphs and also the fT vs Ic graphs.
220uF sounds to big.
220nF or maybe as high as 1uF. Try a low value to be safe.
raitraak said:
Hi
TO-220 MJE150XX is overkill and not too good for the VAS and VAS CCS!
Cheers,
Glen
AndrewT said:2n5551 precedes the VAS as a follower
So what? MJE150XX are still overkill and far less than ideal here.
At least use MJE340/MJE350.
G.Kleinschmidt said:
So what? MJE150XX are still overkill and far less than ideal here.
At least use MJE340/MJE350.
Glen is right.
The VAS due to its configuration as common emitter, cause a distortion (the most known overshoot due to Miller capacitance) which is an intrinsic phenomenon and has relation with the Cob of transistor used, and no so much with the loading of LTP out.
There are Toshibas like 2SC3423 with very small Cob.
The problem with any transistor of any brand, it is that: the lower the Cob, the lower the Ic. For example 2SC3423 has Ic=50mA and Cob=1,8pF. The MJE15030 has Ic=8A and Cob=30pF/150Vr. It is obvious that is an issue related with the machining process of semiconductors. The higher the Ic and Vce, the higher the Cob.
According to the design, there is the need for VAS to operate many times with Ic=20mA and Vce=150Vpp. In this case, 2SC3423 may exceeds its SOA, instead MJE15030 has no problem.
If we see for Toshibas in the same range as MJE15030, for example 2SC5171 it presents almost the same Cob=26pF, a little better which i think does not matters. I realized this because i am busy with solid state designs with high voltage rails (from +/-60Vdc and above) for many years. Yet the MJE15030 as VAS mounted on heatsink with Ic=20mA presents a temp. about 45 deg C, without signal in input.
MJE340/350 are not something special, OnSemi data does not reffer their Cob. We can make an estimation from the next type MJE341: Vce=150V, Ic=500mA, Ft=15MHz, Cob=15pF. Thus MJE340 probably has a worst Cob>15pF, maybe near 20pF. This can offer in practice (observed with a scope) only a negligible improvement in Cdom compared with MJE15030.
Verry nice devices was the Motorola MPS-U10/MPS-U60 (case 152-02) with: Bvce=300V, Ic=500mA, Ft=45MHz and Cob=3pF.... unfortunatelly are obsolete now.
Regs
Fotios
Glen,G.Kleinschmidt said:So what?
help me.
I struggle with the niceties of AC.
Why does the 2n5551 not help reduce the capacitive loading on the LTP stage?
raitraak said:Hey!
Little bump🙂
G.Kleinschmidt, fotios - care to reply to AndrewT?
Regards,
Aq
Aq
I gave a detailed explanation of my thesis... i think so.
I don't disagree that the EF isolates the LTP from the Cdom of VAS transistor. Simply, in my practical tests proved that the Cob of VAS transistor used, it is the main reason for the Miller pole presented on VAS by itself. If the EF between LTP and VAS was an absolute solution, then the compensation capacitor accross the B-C junction of VAS it is uselless... but the capacitor is still presented.
Regs
Fotios
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