It's simple, if it's not for most use cases, it is not a good idea to push that "idea" as global. Especially being said that it's because it's ecpensive it's being shunted away, simply untrue.
On top of that making statements on something not that well designed.
@batteryman Sorry if that ended up being rude, but, the tone was set beforehand, and anything said could be interpreted as harsh.
👍
Clear now. I couldn't imagine that other circuits will be ringing for about 1.3 uS time of inactivity. And this line was confusing:
🙂
Probably not 1.3uS, but who knows?
Before new data and BCK everything has been stable the longest time. Nothing moves.
The 0.5uS or 1uS (TDA1541 datasheet)
Is the time needed for the current change to charge up all parasitics and to then assume the new new value.
Typically this tested with a full scale step. So all bits will be off, diodes reverse biased, switches conducting and we switch all switches off. So we go from 0mA (and 4mA flowing into +5V) to 4mA (and 0mA flowing into +5V).
For this worst case we take a time of "X" for the current to reach within 1LSB of nominal.
Does what happens on BCK influence this time or change the output value if not "silent" during this time? How? There is no physical mechanism for that.
But how comes we see BCK in the Output? Like this?
https://www.mvaudiolabs.com/digital/tda1541-digital-input-attenuation/
From the inputs and probably due to the bad habit of linking AGND & DGND and dumping all sorts of cr@p into this "ground". Plus capacitive coupling into the substrate etc. et al.
Thor
Before new data and BCK everything has been stable the longest time. Nothing moves.
The 0.5uS or 1uS (TDA1541 datasheet)
Is the time needed for the current change to charge up all parasitics and to then assume the new new value.
Typically this tested with a full scale step. So all bits will be off, diodes reverse biased, switches conducting and we switch all switches off. So we go from 0mA (and 4mA flowing into +5V) to 4mA (and 0mA flowing into +5V).
For this worst case we take a time of "X" for the current to reach within 1LSB of nominal.
Does what happens on BCK influence this time or change the output value if not "silent" during this time? How? There is no physical mechanism for that.
But how comes we see BCK in the Output? Like this?
https://www.mvaudiolabs.com/digital/tda1541-digital-input-attenuation/
From the inputs and probably due to the bad habit of linking AGND & DGND and dumping all sorts of cr@p into this "ground". Plus capacitive coupling into the substrate etc. et al.
Thor
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@ThorstenL
I found some spice models for SS9014 / SS9015, used also BC547C / BC557C and MPSA18.
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I rearenged Your IV for negative branch -15V. It is all the same but transcribed only to negative PS side, as this PS is analog. (Circuit have negative grid bias option for direct coupling tube). I just put some JFETs that available for sure that could be better choices in TO-92 there.
.
Please give some comments about currents for BJTs I am not sure thay right?
Thanks.
I found some spice models for SS9014 / SS9015, used also BC547C / BC557C and MPSA18.
.
I rearenged Your IV for negative branch -15V. It is all the same but transcribed only to negative PS side, as this PS is analog. (Circuit have negative grid bias option for direct coupling tube). I just put some JFETs that available for sure that could be better choices in TO-92 there.
.
Please give some comments about currents for BJTs I am not sure thay right?
Thanks.
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BIG (effing) BLINDING FLASH OF THE OBVIOUS!
Again. I'm a moron. I must be getting old. Next time I miss the Portuguese Man of War jelly fish in the Bight of Siam when I go for a swim. That would be very double plus ungood.
Ok, try this...
Output 2V RMS.
Op-Point is fiddly, there is very little leeway for tolerances. I guess best make the CCS adjustable as well.
But we get 2V RMS with "passive resistor only" I/U conversion.
Excellent thinking Zoran.
Thor
PS, one for the haters, just put me on ignore... I'm full on Taylor on all that hate anyway.
Remember, we are the love generation!
Yes with "negative" branch reforming there is much wider room to put higher value of Riv.
,
I did this i must admit, because we have on this way negative grid bias at the Riv and can be proced to tube amplifikation stage.
That is posibile because the circuit giving almost the same distortion values for low , and midlle values of Riv
Coupling without capacitor - direct. No Rk and Ck in the cathode...
Option is to put in the cathode a battery reverse polaritu if You vant smaller negative grid bias.
Also the circuit could be cascaded for even more negtive grid bias without losses.
And with linear tube the final result is still in very low THD and phase is back to 0 deg. 🙂
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i will post some example
Somebody check the biasing of the transistors please?
I am not sure that is correct?
This one from the left with marked values.
Thanks
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I am not sure that is correct?
This one from the left with marked values.
Thanks
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Yup. Great thinking. Wish I had thought of that. I was obsessed with correct current loops. But they all terminate at -15V anyway....
That also works with the I/U conversion resistor to +5V.
Tube cathode referenced to +5V, voila, -2.5V Bias...
Your transistor bias seems ok, I suggest play with the resistor values in the sim and then in the real world.
Thor
Zoran,
Curious about the J310 Jfet model choice. You need all that current, or you picked up them because THT and low noise VS some others THT (J113, J112...) ?
Curious about the J310 Jfet model choice. You need all that current, or you picked up them because THT and low noise VS some others THT (J113, J112...) ?
Hi
I just pick up first that cross into my mind, and knew that it is available in local stores... 🤢. Just for the brief check...
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But better results on the sims are with serial 2 x 2N4391 and +15V supply.
Also famous 2SK170 is very good for +5V, If we dont want additional power supply line...
Probably J111 and J117 are also good on the sims i cant remember now. When used as single, Idss should be higher than Io of CCS...
cheers
Hi
I am interested to buy / build a DAC based on 4/8 TDA 1541. I do NOT possess enough knowledge to understand the details of technology.
Are there ready kits/PCB/circuit diagram available for sale?
Thanks.
I am interested to buy / build a DAC based on 4/8 TDA 1541. I do NOT possess enough knowledge to understand the details of technology.
Are there ready kits/PCB/circuit diagram available for sale?
Thanks.
Thanks Zoran for the circuitry behavior input.
I use often the J113 with its average 15 to 20 mA (the datasheet says 2 mA...) because it's cheap and good enough for my needs. But the J310 is quieter of course (but x13 the price, ouch !)
I use often the J113 with its average 15 to 20 mA (the datasheet says 2 mA...) because it's cheap and good enough for my needs. But the J310 is quieter of course (but x13 the price, ouch !)
Just a comment. J-Fet CCS appear simple, but they cause headaches.
First, variability means we either design to eliminate the need for trimming and accommodate the wide current spread, which in this circuit is not acceptable. Of course, we probably need to trim the CCS anyway.
The other issue is the Tempco, the current is quite drifty.
While I used to use a lot of J-Fet CCS and LED biasing back with early AMR, these proved difficult for consistency, so my preferred solution is now to use bipolar devices and 431 and filter noise as thermal compensation is trivial.
Here you see the frontend, over a 100 degree Temperature change current drifts basically not at all and the input voltage that keeps the TDA1541 pin nominally at 0V drifts only ~ 20uV/K. It could be further improved by current matching in the various transistors, but that makes the relative simple circuits more complex.
The transistors that form thermal cancelling pairs must be closely coupled thermally.
Parts of the reference circuit can be shared between L/R channel. A single T10 could probably be used to drive both CCS transistors with R20 reduced to 7.5k. In this case T10, T6 and the other channel equivalent of T6 must be thermally coupled tightly.
With 10k/1000uF filtering in the CCS (I guess I can use up some of the Nichicon KL I decided against using on DEM now) leads to a 20mHz turnover, so -54dB @ 10Hz, so the 220nV|/Hz noise from the TL431 is squashed to ~0.5nV|/Hz at 10Hz. The transistors are much more noisy at pretty much any frequency except almost DC.
A lower noise reference would be good, but there is not a lot around that is really low noise < 10Hz and stable, bandgaps are noisy, those with build in RC filtering have the LF problems. Other references that are really low noise are not easy to find.
Thor
String of infrared leds maybe? (well layout alert: perhaps the number needed and fragility of the serie behavior, ground loop size decoupling, etc !).
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Above, typical LED temperature drift.
You might be able to match temperature drift so LED and Transistor compensate each other, but it is not, in my experience production reliable.
It may be acceptable for DIY if the person building knows how to compensate different batches, diffusion sites or even different OEM's with different processes for nominally the same part. But I doubt many DIY Enthusiasts are that knowledgeable.
In actual proction it is not feasible. We designed out LED's for zener diodes with more noise, but less other variations and J-Fet CCS for mostly ring of two, which have thermal drift, but usually are acceptable.
Thor
I haven't read all the previous posts but isn't it simpler to use a classic two terminal CCS network perhaps using an JFET and an LM334 per below? The JFET seems adequate to isolate the digital transients from the reference current set by the LM334. Or stack a pair of J111's (IDSS 20mA). By the way, didn't William Marshall Leach publish a work on constant current sources?
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