Your cap and trafo equalises them to equality - those reactive components filter out the differences I would think. Maybe your system, or perhaps the listener, have problem handling the reality!?
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Thanks for the compliment!
Indeed. Making the FIRDAC longer would reduce the effect of far-off phase noise and clock spurs, which shows that at least one further improvement is possible. I have no reason at all to assume that's the only one.
Indeed. Please keep in mind that SRCK runs at twice the bit clock frequency.
Yes, but do keep in mind the doubled clock, and that the delay between the taps is therefore only half a bit clock cycle. One can therefore regard the first and third outputs of a four-bit shift register as a two-tap RTZ FIRDAC and the second and fourth outputs as a half-cycle-delayed (a.k.a. interleaved) copy.
If one would reduce the length of the shift register to two sections and make it multibit, one would have the exact same waveforms as in the 1997 patent you quoted recently: an RTZ signal coming out of the first tap and a half cycle delayed copy coming out of the second tap. As the length is more than two sections and the wordlength is only one bit, it is more like the 1990 patent I quoted.
Indeed. The TI SN74LVC1G74 inverting flip-flop output had slightly more favourable timing specifications, which is the one and only reason for using the inverted output and OR instead of NOR gates. The delay is specified as 1.4 ns to 4.1 ns from CLK to Q at 5 V, 1.6 ns to 4.4 ns from CLK to QN. As the hold time requirement of the shift register is 1.5 ns, the latter is theoretically better.
However, these specifications only hold with a lumped 50 pF load which is nowhere to be found in my design, and besides, because of unavailability of TI parts, I actually used Nexperia parts. The Nexperia 74LVC1G74 has a 1 ns to 4.1 ns spec for both Q and QN, so I might as well have used NOR gates and the uninverted output after all.
Measurements from @Markw4 showed that the typical hold time was too close for comfort to the requirement. I later fixed that with increased values of R124, R127, R129 and R131 (270 ohm, see post #1).
The clock frequency matters.
That's very well possible.
Definitely. It's only unfortunate that the discussion doesn't seem to converge.
I assume you mean US patent 4947171 ( https://patents.google.com/patent/US4947171A/en ), as US patent 6061010 is very explicitly return to zero.
Figure 2 of US4947171A is non-return-to-zero, but Figure 5 shows the basic idea behind return to zero. Figure 6 is a return-to-zero FIRDAC with half-cycle delays between the taps, so with interleaving between the odd and the even taps. That's conceptually precisely what I use in the circuit of this thread, the CMOS logic gate DAC and the valve DAC, although implementation details are different. The biggest difference is that US4947171A has the gating after the shift register, implemented in current steering logic. I had the gating after the shift register in my logic gate DAC and valve DAC, the latter using current steering logic, but put it before the shift register in the design of this thread.
A flip-flop normally consists of a cascade of two latches driven by inverse clocks, so tapping off the data from each latch is straighforward on an IC, particularly when the flip-flops are designed at transistor level rather than taken from a standard cell library.
I think I explained the advantages (and disadvantages) of RTZ at various places.
Regarding clocking an RTZ FIRDAC with half-clock-cycle delays with a frequency-doubled clock or with a two-phase, not doubled bit clock:
When a clock signal with nonzero rise and fall times goes through a slicer with an inaccurate slicing threshold, the duty cycle at the slicer output is affected by the actual threshold. Very rough and grossly exaggerated sketch:
Suppose you have a slicer that produces a high level when the green signal exceeds the lower dashed line. The output signal will then be a 50 % duty cycle square wave.
When the threshold changes from the lower dashed line to the upper dashed line, the duty cycle of the slicer output decreases. It's interesting that, with these symmetrical rising and falling slopes, the centre of the output pulse doesn't shift, only its width changes. As a result, small threshold shifts affect the duty cycle (and the locations of the rising edges) more than the phase of the fundamental.
A small CMOS logic gate behaves as a slicer of which the slicing threshold varies randomly with time due to the 1/f noise of the transistors in the gate. Hence, it causes duty cycle modulation with 1/f noise - as well as with white noise, but 1/f noise is particularly bad in small MOSFETs. This 1/f noise has only little variation from clock cycle to clock cycle, but does vary over audio time scales.
An inaccurate duty cycle of the bit clock to the whole DAC changes the ratio between the pulse widths of the odd and even taps, but (ideally) doesn't change the average output signal. That is, the DAC is not particularly sensitive to low-frequency variations of the duty cycle of the bit clock to the whole DAC.
For a scheme with a doubled clock, the same holds for anything that slowly shifts the rising edges of the doubled clock, such as 1/f noise in the circuitry after the clock doubler. The falling edges don't matter at all (in principle anyway) as long as the timing requirements are met.
For a scheme with a clock and a clock with inverse polarity clocking the odd and even stages, duty cycle variations of these two clock signals directly affect the gain of the DAC and therefore modulate the audio signal with 1/f noise. In a single-ended version, they also modulate the DC bias voltage, so you also get 1/f noise of the clocking circuitry being converted to 1/f noise at the output.
Because of this, I would like to keep as much clocking circuitry as possible common to the odd and the even taps. Hence my preference for a common, doubled clock. I did use a two-phase, not doubled clock in my logic gate DAC and valve DAC, by the way.
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This little expose' is fascinating (even if repeating previous talking point.
My aim is actually to a much lager step back.
Let me first confirm we agree on the following assertion:
"The schematic shown below, will, on a macro level perform identical (output levels, FIR Filter frequency response) accounting for minor differences due to precise resistor values."
Now, presuming agree on this, I would propose the following adjustment:
We now have two parallel output 4 bit FIR DAC's with independent Data inputs.
Now, completely independently I also propose to make the Clock input's of U19/25 switch selectable between "clock" and Gnd (0) to allow both RTZ/NRZ to be selectable.
I do not necessarily propose to actually do this on real PCB's, just for our analysis.
We can now explore easily (in concept or simulation) the following configurations and see what the relative benefits and disbenefits of each configuration are.
Default is:
Dual Balanced Return To Zero (DBRTZ)
Alternatives are:
Dual Balanced No Return to Zero (DBNRZ) [same as default in NRZ]
Series Return To Zero (SRTZ) [both sections daisy chained to make an 8 Bit FIR DAC, RTZ signal]
Series No Return to Zero (SNRZ) [both sections daisy chained to make an 8 Bit FIR DAC, NRZ signal]
Interleaved Return To Zero (IRTZ) [sections interleaved to implement a "Dual return-to-zero pulse encoding in a DAC output stage"]
I would propose that each configuration is valid in principle and offers a different set of trade-offs between Inter Symbol Interference (Rejection), Jitter Sensitivity, Output levels and thus SNR, clock related ripple on the reference voltage and clock ripple feedthrough into the output.
I for one would suggest that perhaps one of these configurations can offer improvements over the default in one and possibly several metrics and it is probably worthwhile to see if there is such an improvement, or shall we define it as a more favourable trade-off of the different metrics than the default.
Given that the required "re-design" amounts to shifting two connections around, I for one would consider it worthwhile to do such an evaluation. It is actually relatively trivial and can be done with nothing more challenging than pen and paper.
At the best case such an evaluation will confirm the default as the best option and validate the design choices and at worst it will allow improvements to an already good design. I cannot see really any problem here.
It MAY also be of interest to some of the readers to carry out such experiments on actual hardware and to have a listen.
Again, if this in not a discussion that is valid here, let me know and I will say no more.
If not, perhaps when time allows, I will look into the individual cases.
Thor
Be my guest.
By the way, when you short pin 1 of U28A to its supply, you halve the clock frequency and change to non-return-to-zero with just one extra wire. It will probably sound better like that, because the volume increases.
By the way, when you short pin 1 of U28A to its supply, you halve the clock frequency and change to non-return-to-zero with just one extra wire. It will probably sound better like that, because the volume increases.
IME it won't sound better. I can do the same thing with Andrea's DSD dac by changing the FPGA configuration which results in the same type of volume change. Don't know why people think everyone would always be fooled by obvious volume level changes. Its when the volume level changes are too subtle to be obvious that it can get tricky.
Not long ago you yourself were fooled by playing almost identical recording at 2dB lower level and claiming it "sounds like a muddy, dynamic compressed copy, with lost imaging".
No, I didn't. I already told you what happened.
The real issue back then was with those crappy copies with the excessive loss of HF compared to the original. The description, "sounds like a muddy, dynamic compressed copy, with lost imaging," actually applies to the copies as compared to the original, and it is an apt description of the difference. You never did explain how your carefully measured ADC and DAC could make such a bad copy? Now we know we can't trust your measurements as meaningful.
The real issue back then was with those crappy copies with the excessive loss of HF compared to the original. The description, "sounds like a muddy, dynamic compressed copy, with lost imaging," actually applies to the copies as compared to the original, and it is an apt description of the difference. You never did explain how your carefully measured ADC and DAC could make such a bad copy? Now we know we can't trust your measurements as meaningful.
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Based on what you posted you did. What you told us afterwards was that you accidentally listened to a version with 2dB lower level. But you still cockily made the claim of the difference without realizing what was the cause. Nobody else found those copies crappy and you did not show any evidence for your claims. What that actually proved is that your listening evaluations cannot be trusted as you clearly have trouble matching levels or to even realize that levels are 2dB off.
Calling the copies crappy when no one else could reliably tell the difference against the original does not indicate that your listening prowess or your system is superior. It actually does the opposite and casts a long shadow on your listening evaluations claims.
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Merci beaucoup!
I guess that is an option. I would have instead included a NC7SZ157 into the circuit instead between U28B out and clock inputs of U19/25, to avoid to hanging capacitive loads and switches off clock nodes.
Mind you I suggested this not necessarily as something to be done in practice, but as a thought experiment.
However I feel that there are relative tradeoff's between NRZ and RTZ that need to at least considered.
It is not "RTZ = GOOD" and "NRZ = BAD", which is on the same level as idology as "4 legs good 2 legs bad" from Orwell's Animal farm.
Rather NRZ and RTZ both offer desirable and undesirable traits, however, it SEEMS that it is NOT POSSIBLE to combine the desirable traits of NRZ with those of RTZ while not introducing additional undesirable traits.
But maybe it ONLY SEEMS IMPOSSIBLE and in reality is eminently possible?
If so, is it not worth investigation (answers muttering to himself - of course not, this is the post truth, post science age where it does not matter what is right, instead it matters how it makes some feel).
When doing such experiments for listening it is obviously essential to compensate level differences greater than the agreed minimum audibility threshold (usually held to be 0.1dB but I am open to solid evidence to alter this), to be valid.
I make a basic assumption that valid scientifically conducted tests (even simple sighted listening) will demonstrate correct level matching. I usually ask if this was done prior to making comments.
Thor
One advantage of NRZ is its reduced sensitivity to far-off phase noise / jitter and spurs (not to close-in phase noise). This can also be achieved with RTZ when you use a FIRDAC of twice the length that you would have used for NRZ and give it half bit clock cycle delays between the taps, such that the odd and the even parts work in an interleaved manner (as is done in the DAC of this thread).
You also need twice the FIRDAC length to suppress idle tones with RTZ and half-bit-clock-cycle delays. For example, with uniform weighting, you need a FIRDAC of length 2 with NRZ and length 4 with RTZ with half cycle delays to suppress idle tones around half the sample rate.
Hence, I come to these advantages of NRZ:
A. Half the FIRDAC length needed compared to RTZ with half-bit-clock-cycle delays
B. Lower transition density, may be an advantage when there is a settling issue
C. Somewhat simpler circuitry
D. Twice the output signal amplitude at a given reference voltage
and these disadvantages of NRZ:
A. The intersymbol interference issue that causes increased noise floors and intermodulation products between idle tones around half the sample rate.
B. I see no straightforward way to keep the reference current independent of the data pattern, so keeping the reference clean will be more problematic.
You also need twice the FIRDAC length to suppress idle tones with RTZ and half-bit-clock-cycle delays. For example, with uniform weighting, you need a FIRDAC of length 2 with NRZ and length 4 with RTZ with half cycle delays to suppress idle tones around half the sample rate.
Hence, I come to these advantages of NRZ:
A. Half the FIRDAC length needed compared to RTZ with half-bit-clock-cycle delays
B. Lower transition density, may be an advantage when there is a settling issue
C. Somewhat simpler circuitry
D. Twice the output signal amplitude at a given reference voltage
and these disadvantages of NRZ:
A. The intersymbol interference issue that causes increased noise floors and intermodulation products between idle tones around half the sample rate.
B. I see no straightforward way to keep the reference current independent of the data pattern, so keeping the reference clean will be more problematic.
Marcel, this is the second time you asserted that the current DAC works "interleaved".
To be clear, we are referring to this DAC:
Right?
Second MY definition of interleaving is this (ignoring the binary weighting in the patent this is sourced from):
I do not see how we get the data to the second FIR DAC delayed by 1/2 clock2f, the second DAC received the same data as the first.
Thus we have the situation (for macro level behaviour) that I asserted before and that you have not falsified or rejected (GFX reworked for more clarity):
IF we wanted to create an interleaved RTZ DAC, in my view, we would need to use this schematic:
Now, I will still not exclude the possibility that I am just to stupid to understand how interleaving works in this DAC:
As said, I'm not very smart. So I asked about this before. What is interleaved where - to achieve the claimed benefits?
Thor
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Deltawave was used to compare one of the copies with the original (which are the two files I actually listened to, despite a previous misstatement to the contrary). Playback of the delta between the two files clearly shows excessive HF loss in the copy which is so far unexplained (and which is easily audible on a good system). Until the problem is found and fixed any results from your ADC/DAC system will remain suspect.
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The files themselves have no HF loss whatsoever. If you hear a HF loss it only means that your system or your hearing is the cause especially since no one else has reported this.
Your claim about HF loss which is nowhere to be seen on recorded data just shows that you are grasping at straws.
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Deltawave showed the original file and one of the copies when compared have a difference in HF content. The difference between the original and the copy can be heard if the difference signal is played back by Deltawave through a reproduction system. Apparently you don't understand how to use Deltawave to compare the original music file and a copy file produced by your DAC/ADC.