Yes, the core is never perfectly linear, just like transformers. So some form of zero field operation is desirable.
Like zero ohm source, infinite load or Infinite impedance source and zero ohm load.
In my case I used low source impedance and relatively high load impedance. And Bias and "chonky" inductors.
See here for more on distortion and inductors...
Thor
That seems to be based on a misunderstanding The farther you move from the zero crossing, the stronger the hysteresis.
Hans
I should have stated hysteresis distortion...
The greater the DC bias the smaller the minor loop, as area between the two curves narrows.
Thor
PS, Hans please note I have you on ignore, so if you reply and do not get reply back it is because I normally do not see your responses.
This is very possible. Measurement artifacts.
BTW, I stumbled across this. Not sure if it is of any value to those who do their own modulators, like Pjotr and Marcel, so I'll just drop it in here, as we do discuss these in passing.
Audio Engineering Society Convention Paper - Simple, Ultralow-Distortion Digital Pulse Width Modulator
Thor
In your second picture, the core is driven halfway to saturation. (The associated inductance loss will actually still be small in a core with an airgap.) I didn't realize you were referring to DC currents large enough to do that. For power inductors, it may take amperes rather than a milliamp or two.
Regarding modulators, there is some more recent work of possible interest, but too large to attach here.
https://www.dropbox.com/scl/fo/mb53...C3bfbYhQ?rlkey=15v1k5o04r9j0bkd92ifhrfpp&dl=0
https://www.dropbox.com/scl/fo/mb53...C3bfbYhQ?rlkey=15v1k5o04r9j0bkd92ifhrfpp&dl=0
Even a smaller current shifts the minor loop. It's all a question how much and what inductor is in use, which in turn depends on circuit impedance's.
My application was an 80kHz RCLC filter terminated into 10kOhm.
Thor
I mentioned interleaving RTZ DAC's before and I think we never got on the same page.
I finally located the Patent I had found before:
Dual return-to-zero pulse encoding in a DAC output stage
This may clear up any misunderstanding we had before regarding this.
Thor
I finally located the Patent I had found before:
Dual return-to-zero pulse encoding in a DAC output stage
This may clear up any misunderstanding we had before regarding this.
Thor
Because of Marcel's (dual) 2 bit voltage Firdac structure, IMO this patent does not have any application here.
Hans
Hans
I think it does, except that I combine it with a FIRDAC, as described in patent Heinrich Pfeifer, Werner Reich and Ulrich Theus, Circuit arrangements for averaging signals during pulse-density D/A or A/D conversion, US patent 4947171, 7 August 1990. It's remarkable that patent US6061010A ever got granted, as they just use a subset of the tricks described in the seven years older patent US4947171. Maybe it's because the earlier patent was about single-bit DACs? Anyway, the patents have both been expired for a very long time.
O.k. I’ll read the patent that you referred to.
In the meantime I tried to simulate the interleaving and found only a increase in output of 6dB, but no increase in S/N.
Hans
Without interleaving, mind you.
If we want to be bloody minded the circuit that AD's patent describes also does not really qualify as "RTZ" as is current steering, so the "Zero" part is actually "no current" while the "One" part means current is flowing. As Zero = "open circuit" calling it "RTO" is more appropriate IMNSHO.
It frequently boggles my mind too. I took the time to figure it out about a very different patent. This patent is for "The World's best Loudspeaker".
http://www.worldsbestloudspeakers.com/
That "thing" was a certain enclosure (basically a smallish small floor standing tower) with a 5" X 8" car 3-Way coaxial driver, not something branded and nice, but the nastiest cheapy from the far east.
It sounded rather underwhelming even after a lot of EQ courtesy of Behringer DEQ2496:
Yup, 15dB attenuation needed around 1kHz and 15dB boost below 40Hz. Anyway, this digresses.
It foxed me and I pursued the patent and I could not understand what was being patented. The enclosure was actually a verbatim copy of Vivian Capel's "Kapellmeister" (a design from a UK DIY Speaker Book from 1988) not made from wood or wood composite but instead using sheetrock (gypsum sheets) on a wood frame. Don't drop that speaker. As the original "Altai" Brand car speaker was long off the market whatever was bolted in was substituted.
The source of the enclosure was given, in the patent. It's Patent GB2399473 which seems withdrawn, I cannot locate it now. I could not get how the patent was granted, and what was being patented. Claims were like 30.
So I was clueless but down at the Pub I knew a guy who about this stuff, so I asked him. It took him a bit as well, but he eventually figured it out.
The patent claimed that making the specific open source enclosure design (and only this - no other) using sheetrock and not wood composites and using it with the specific driver used as unique and independent work and it was granted on the principle that while speaker enclosures had been made from all sorts of materials and patented, nobody had made THIS enclosure from THIS Material (sheetrock) and used this driver.
It was written so as to seem to claim almost any speaker and speaker feature under the sun but actually once distilled by a patent pro the actual claim was extremely narrow and even so could have been challenged under obviousness. I think it was a gross abuse of the British Patent System, which compared to the US is relatively circumspect in grants.
Indeed. I did not mean to suggest any patent infringement but instead to illustrate.
More specifically to illustrate this:
More specifically the "SUM waveform trace".
While this shows a binary weighted DAC, it can be applied equally to unitary weighted FIR DAC.
It would be relatively trivial to achieve this style of interleaving with your DAC if we delay one half of the FIR DAC appropriately, all the hardware needed is already there.
Thor
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@marcel,
As far as I understand in this patent, instead of operating the shift registers with one clock, the shift registers are alternatively clocked with the clock and its inverse, thereby reducing the error on the summed signal caused by the clock jitter.
But in case of this patent no RTZ is applied.
This is different from what I simulated, where I added two RTZ signals shifted a half clock cycle but still by operating the shift registers with one clock.
Now the question to you, what are the expected benefits/drawbacks of your RTZ version with shift registers all on the same clock, versus a non RTZ version with the shift registers being operated by a two phase clock ?
Instead of using the two existing shift registers being clocked by the same clock, they could just as well be operated by a dual phase clock.
Without paralleling, one could even create 8 outputs, thereby reducing the clock jitter even further.
Hans
As far as I understand in this patent, instead of operating the shift registers with one clock, the shift registers are alternatively clocked with the clock and its inverse, thereby reducing the error on the summed signal caused by the clock jitter.
But in case of this patent no RTZ is applied.
This is different from what I simulated, where I added two RTZ signals shifted a half clock cycle but still by operating the shift registers with one clock.
Now the question to you, what are the expected benefits/drawbacks of your RTZ version with shift registers all on the same clock, versus a non RTZ version with the shift registers being operated by a two phase clock ?
Instead of using the two existing shift registers being clocked by the same clock, they could just as well be operated by a dual phase clock.
Without paralleling, one could even create 8 outputs, thereby reducing the clock jitter even further.
Hans
I can only conclude that you still don't understand how my DAC works. It's a pity, but so be it.
Not to be rude or anything, but I'm not sure any of us fully understand how Marcel's dac works. For me, I still find no matter what I have tried so far I can never get it to sound as good in differential output mode as I can in SE output mode. Not saying I won't keep trying, but the results have been pretty consistent so far. Seems me there must be some 2nd order effects or something complicating the differential output should be best theory.
I also had that opinion, but then Marcel’s remark made me unsure.
Maybe I misinterpreted his comment.
Hans
First, I think this RTZ DAC shows that compared to NRZ FIR DAC's (e.g. DSC) improves materially on existing DIY designs. Such advances always raise the question of "can we do even better" and "If we can, how might we". We have looked at modulators and analogue stages and found potential improvements, surely the original DAC itself is not a "holy cow"?
Well, I am pretty stupid, that if for sure. I need to really have things explained to me like I am an idiot (I am). I will enunciate my personal lack of understanding of how this DAC works, by explaining my understanding (this is strictly about page 3/4 in the DAC3_10 Document).
I see a single clock applied to all shift registers (SRCK from here on).
I further look and see that we have a total of 16 Flip Flops, connected as four shift register chains of four. I further see that the four shift register chains are configured as two balanced four bit chains that operate in parallel.
The arrangement of using double the number of nominally balanced circuits in parallel with the polarities to one balanced block flipped is used to overcome assumed or actual systemic physical asymmetries in a balanced circuit (as have been postulated, but not demonstrated for the shift registers in use) and is often described as double balanced.
In principle each 74XX574 forms a complete balanced 4-Bit FIR DAC. There are no delays or different clocks between separate DAC sections or anything of the like.
On a Macro level removing one shift register IC and replacing the 3.06k resistors on the remaining Shift Register IC by 1.5k will obtain identical results ON A MACRO LEVEL (first / second order effects). I do appreciate that glosses over some subtle differences between the configurations, hence the "macro level identical" qualification.
From analysing the circuit on page 5 I know that the shift register chains are fed with balanced single bit data (created in U21/23) and having every second shift register clock a forced one inserted in the data on both balanced data lines (via U19/U25 OR Gates) which are then flipped between polarities, relocked (in U22/24/26/27) and polarity inverted by using Qbar output from the relocking Flip Flops.
I would suggest that replacing U19/25 with NOR Gates (and adjusting the rest) avoids the flipping polarities around multiple times and makes the operation more clear conceptually, as the multiple polarity inversion had me foxed initially. It would however not change the actual outcome.
I further look and observe that as a result of all the above we have a classic RTZ DAC structure with all the benefits and drawbacks of such.
The same DAC hardware (page 3/4 could also run NRZ with all the NRZ benefits and drawbacks of such. No change is needed to the DAC Hardware (page 3/4) for RTZ or NRZ operation.
This is ultimately down to the upstream logic which does not, as such concern us for the specific sub topic.
I would greatly appreciate if the flaws in my understanding and reasoning so far could be made clear, so I can improve my understanding of basic digital logic, as it seems I have missed something important and fundamental.
I finally observe that the existing hardware can, with extremely minor modifications, be used in a number of alternative connection options for the second 4-Bit SR DAC, that will allow us to make alternative trade-off's between a range of parameters (and potential or actual fidelity impairments) with the same hardware.
Perhaps I am not understanding anything, however looking from my very limited understanding, I can see a potential for alternative configurations to improve performance over the baseline in some areas and quite materially so (we are after all dealing with first order effects) and at least I personally feel that discussing such is as valid as discussing analogues stages.
However, if such a discussion is off limits here, I will respect that and speak no more.
Thor
Well, I am pretty stupid, that if for sure. I need to really have things explained to me like I am an idiot (I am). I will enunciate my personal lack of understanding of how this DAC works, by explaining my understanding (this is strictly about page 3/4 in the DAC3_10 Document).
I see a single clock applied to all shift registers (SRCK from here on).
I further look and see that we have a total of 16 Flip Flops, connected as four shift register chains of four. I further see that the four shift register chains are configured as two balanced four bit chains that operate in parallel.
The arrangement of using double the number of nominally balanced circuits in parallel with the polarities to one balanced block flipped is used to overcome assumed or actual systemic physical asymmetries in a balanced circuit (as have been postulated, but not demonstrated for the shift registers in use) and is often described as double balanced.
In principle each 74XX574 forms a complete balanced 4-Bit FIR DAC. There are no delays or different clocks between separate DAC sections or anything of the like.
On a Macro level removing one shift register IC and replacing the 3.06k resistors on the remaining Shift Register IC by 1.5k will obtain identical results ON A MACRO LEVEL (first / second order effects). I do appreciate that glosses over some subtle differences between the configurations, hence the "macro level identical" qualification.
From analysing the circuit on page 5 I know that the shift register chains are fed with balanced single bit data (created in U21/23) and having every second shift register clock a forced one inserted in the data on both balanced data lines (via U19/U25 OR Gates) which are then flipped between polarities, relocked (in U22/24/26/27) and polarity inverted by using Qbar output from the relocking Flip Flops.
I would suggest that replacing U19/25 with NOR Gates (and adjusting the rest) avoids the flipping polarities around multiple times and makes the operation more clear conceptually, as the multiple polarity inversion had me foxed initially. It would however not change the actual outcome.
I further look and observe that as a result of all the above we have a classic RTZ DAC structure with all the benefits and drawbacks of such.
The same DAC hardware (page 3/4 could also run NRZ with all the NRZ benefits and drawbacks of such. No change is needed to the DAC Hardware (page 3/4) for RTZ or NRZ operation.
This is ultimately down to the upstream logic which does not, as such concern us for the specific sub topic.
I would greatly appreciate if the flaws in my understanding and reasoning so far could be made clear, so I can improve my understanding of basic digital logic, as it seems I have missed something important and fundamental.
I finally observe that the existing hardware can, with extremely minor modifications, be used in a number of alternative connection options for the second 4-Bit SR DAC, that will allow us to make alternative trade-off's between a range of parameters (and potential or actual fidelity impairments) with the same hardware.
Perhaps I am not understanding anything, however looking from my very limited understanding, I can see a potential for alternative configurations to improve performance over the baseline in some areas and quite materially so (we are after all dealing with first order effects) and at least I personally feel that discussing such is as valid as discussing analogues stages.
However, if such a discussion is off limits here, I will respect that and speak no more.
Thor
To the above I would add the following observation: Regarding the present states of Marcel's RTZ dac (in fully stock form, sans Marcel's output stage) and my Andrea Mori dac operating in RTZ mode (with the Andrea dac somewhat modified by me), both dacs sound VERY similar to the extent that most of the subjective difference between the sound of the two depends more on which clocks I use with them than to the degree of any intrinsic difference between the sound of the dacs themselves. Please note that both dacs are using the same SE output stage topology consisting of DC blocking caps followed by a 1:1 line level transformer. There is also a difference in volume level between the two dacs which appears to be due to differing Vref voltage levels. I would add that both dacs are capable of sounding very good as judged by several listeners. That includes a deep, detailed soundstage, and a warm non-recessed midrange sound.
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