I assembled the board manually in 2 days, using microscope and hot air despite of my bad vision. But you have to be capable of handling 0402 parts 🙂.
The FFT skirts depend mostly of the window used and the number of FFT points.
In order to verify system jitter professionally, you need to use complicated setup and very good tools.
Visible spurs and very wide skirts around carrier indicate only catastrophic flaws in the performance.
Did you notice any bad on the spectrum presented in the first post?
The noise floor of my design is completely defined by the thermal noise of the LPF.
There is no reason to worry about the noise of FIRDAC resistors, because of it is an order of magnitude lower.
And as I mentioned, it was a tradoff, I needed a DAC of Mola-Mola audio performance just for $300.
Probably ES9039 can achieve it, and even for much lower price, but it is no fun in designing such a thing, buy it on Aliexpess.
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Not good enough resolution in the first post image to say. Given you are using a programmable clock, and an-unknown-to-us reference voltage regulator scheme, I would expect there is room for improvement. Of course this is only applicable if you want to compete are perceptual sound quality to aid sales in high end market. If you don't care about such things then it may not matter.
The reason I mention these things is because there is already experimental evidence that some characteristics of sound are audible to some fraction of the population even if there are not published thresholds for them.
The reason I mention these things is because there is already experimental evidence that some characteristics of sound are audible to some fraction of the population even if there are not published thresholds for them.
The FIRDAC resistors will produce some signal-correlated noise, since excess noise is mostly current noise. It is much more audible to humans than a fixed noise floor. Around a decade ago ESS (the dac maker) gave a presentation where they talked about some of what they know audiophiles are hearing from dacs. IIRC, ESS claimed the human ear is "exquisitely sensitive" to signal-correlated noise. Also, the effect ESS described has been experimentally observed in FIRDACs here, based on choice of FIRDAC resistors.
Thanks George,ska
Congratulations for your creation
Specs in your 1st post look very-very good.
I think if you increase the output to some 2Vrms and improve the SNR as you say, you will have won the numbers game.
If you add a USB input, you' make your DAC as versatile as most here.
George
High SNR is very difficult thing to achieve, and very questionable for audio. For example my LPF has only 6uVrms noise.
With 1Vrms output it provides me exactly -104dB noise floor. But my power amplifier has standard +24dB of gain.
So, using full dynamic range, it needs to be use crazy loud. My neighbors will call a police. 🙂
But if I use volume control at low volume, the effective SNR of the system will be very poor.
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As far as the phase noise is not correlated to audio, I don't care.
There is no point for fighting it. Only if you need >140dB of the real dynamic range.
My DAC sounds very well without that, and provides 142dB SFDR (Spurious Free Dynamic Range).
If there is any jitter dependent correlation, it should be seen as low level THD or spurs, but I can't see any.
The visible residual THD may come from many equivalent sources that difficult to control, like A/D, OPamps, connectors, and etc.
It is correlated to audio. That is exactly the reason for looking at it. The problem of phase noise is well understood in radar, where a lot of money has been spent on the problem. Less understood in audio, but basically it is a correlated noise problem either way. Similar for Vref noise. It is multiplied by the audio signal in the FIRDAC. They become intermodulated and thus correlated.
It is that a dac needs a time reference and a voltage reference. Phase noise is time error, and Vref noise is amplitude error. They both show up as widened spectral line skirts in the frequency domain.
The FIRDACs, designed by professionals are extremely good (Mola-Mola). The problem observed in FIRDACs here is mostly ISI !!! Even in RZ versions.
Another issue is the layout - completely ignoring Faraday low, it rules all RF circuitry, DACs definitely are ones.
Anyway, any signal-correlated noise is THD, it is a simple math.
No correlation - no THD.
A good example - quantization noise and dithering to get rid of it.
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Here is what Sean Olive says about THD:
Here is what Dr. Earl Geddes says about THD:
Our conclusion; people are satisfied with THD and IMD. It’s like the story of the cop who asks a drunk under a street light what he is doing on his hands and knee’s. The drunk replies “I’m looking for my car keys.” The officer asks “Where did you loose them?” and the drunk replies “Over there by my car.” Baffled, the officer asks “Then why are you looking for them here?” to which the drunk replies, “Because the light is better.” Everyone knows that THD is meaningless, but it’s easy to do and “the light is better.”
...
The bottom line here is that we know so little about how humans perceive the sound quality of an audio system, and in particular the loudspeaker, that one should question almost everything that we think we know about measuring it.
http://www.gedlee.com/Papers/papers.aspx
The point of the above it that THD is meaningless as a useful metric in audio. Some HD/IMD is much more objectionable that others. We are trying to help you out here with the more objectionable stuff, and you just want to argue about what was outdated in 1938.
Sorry what kind of jitter you warry about? SPDIF inter-symbol-interference or phase noise of the oscillator?
The J-test that I know, is for SPDIF (or other self-synchronized serial code) only, and it is very-very rough.
Ok, I'll try if I find a time.
"It is not a scientific argument, about policemen and drunks."
There is supporting science. The "drunk under the streetlight" is about human psychology. It is a well known problem in science, even if you are not familiar with it.
https://en.wikipedia.org/wiki/Streetlight_effect
"All empirical research is opportunistic – at least to some degree. We tend to focus on topics for which data and methods are readily available. There is a widely employed metaphor used to describe research that focuses on accessible topics to the exclusion of other important avenues of research, suggesting that you are searching for your car keys under the streetlight."
https://www.sciencedirect.com/science/article/pii/S0306919220301585
There is supporting science. The "drunk under the streetlight" is about human psychology. It is a well known problem in science, even if you are not familiar with it.
https://en.wikipedia.org/wiki/Streetlight_effect
"All empirical research is opportunistic – at least to some degree. We tend to focus on topics for which data and methods are readily available. There is a widely employed metaphor used to describe research that focuses on accessible topics to the exclusion of other important avenues of research, suggesting that you are searching for your car keys under the streetlight."
https://www.sciencedirect.com/science/article/pii/S0306919220301585
J-Test has nothing to do with SPDIF. It is meant to stimulate data jitter.
I don't have any worries about your DAC but if you intend this thread to a be showcase of its capabilities the picture in your 1st post does not tell much. Your DAC uses VCXO and Toslink both of which are not generally considered ideal for low jitter.
Yes, of course, my approach to Hi-End is heretic one. I'm an industrial engineer and former Soviet scientist.
1. TOSLINK is the best way to get rid of ground loops.
2. SMPS is the best way to get rid of mains hum.
3. The VCXOs I used are not the best, but acceptable choice. BTW, FIRDAC reduces phase noise by 1/sqrt(N) times.
4. My presentation was very brief, I apologize. But I mentioned a 0.03Hz bandwidth of the Digital PLL of 3-rd order, implemented in FPGA.
At the frequency +_10Hz from carrier it provides about -100dB of additional filtering. It take ~45 seconds to stabilize the loop filter.
The effect is exactly the same as ASRC, but a way simpler to implement.
Any artifacts of SPDIF usage should be eliminated by design of the PLL control loop.
If I find some time, I'll do further verification, but for now, I need to get back to work. Sorry.
1. TOSLINK is the best way to get rid of ground loops.
2. SMPS is the best way to get rid of mains hum.
3. The VCXOs I used are not the best, but acceptable choice. BTW, FIRDAC reduces phase noise by 1/sqrt(N) times.
4. My presentation was very brief, I apologize. But I mentioned a 0.03Hz bandwidth of the Digital PLL of 3-rd order, implemented in FPGA.
At the frequency +_10Hz from carrier it provides about -100dB of additional filtering. It take ~45 seconds to stabilize the loop filter.
The effect is exactly the same as ASRC, but a way simpler to implement.
Any artifacts of SPDIF usage should be eliminated by design of the PLL control loop.
If I find some time, I'll do further verification, but for now, I need to get back to work. Sorry.
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If clock generation is fully independent from data, any manipulations with data are useless for evaluation of the phase noise.
It is obvious fact.
Oscillator PN depends only on its internal design and on power supply quality.
There are, of course, some sort of data dependent delays and logic levels modulations, that may trigger clock dependence on content of digital audio-data. It is another story, called aperture jitter of digital circuitry.
It should be mitigated by proper decoupling, differential clocking and some other means. It's all about Fast Logic Design black magic.
See your PC motherboard for reference 🙂.
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