and very successfully IMO, given that I've been able to successfully build two examples so far, with excellent resuts.
I will consider both
Send the prototype to Mark first to get things going.
Enjoy your summer activities …
When your are ready in good time, assemble and test a new unit and then we can think about what to do next.
Thank you so much!
The user manual is here: https://www.minidsp.com/images/documents/MCHStreamer User Manual.pdf
It looks like there is a 12 pin header, which is multipurpose depending upon the configuration. In 8 channel DSD mode, it provides eight single channel DSD bitstreams, two clocks (MCLK, BCLK), a pin that's always high when sending DSD, and a ground reference.
From the manual (edit: page 16, stereo DSD, page 26, 8 channel DSD):
MCLK: The master clock for both playback and recording.This pin is always an output. Connected circuitry can choose whether or not to use it.
BCLK: The bit clock. This clock corresponds to the bit rate of the DSD signal i.e. 64 x 44100 Hz for DSD64, and so on.
At DSD256, the MCLK rate is 22.5792 Mhz, and the BCLK rate is 11.2896
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I'm looking at DAC3.pdf. This is genius stuff @MarcelvdG
I'm (way) outside of my pay grade, but would it be possible to fan out BCLK, and connect pairs of the dsd bitstream outputs and the common BCLK to pins 1,3 and 7 of CONN_02x04 on each unit, with decent/good results?
If that works functionally, I'm guessing the quality of the clock is going to be an issue (but I'm in the process of understanding DSD )
I'm (way) outside of my pay grade, but would it be possible to fan out BCLK, and connect pairs of the dsd bitstream outputs and the common BCLK to pins 1,3 and 7 of CONN_02x04 on each unit, with decent/good results?
If that works functionally, I'm guessing the quality of the clock is going to be an issue (but I'm in the process of understanding DSD
)
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After seeing the header connections, I share Mark's concerns about the purity of the clock. Pushing eight DSD signals and the clocks through a common header with only one ground pin is asking for crosstalk from the data to the clocks.
I'm looking at DAC3.pdf. This is genius stuff @MarcelvdG
I'm (way) outside of my pay grade, but would it be possible to fan out BCLK, and connect pairs of the dsd bitstream outputs and the common BCLK to pins 1,3 and 7 of CONN_02x04 on each unit, with decent/good results?
If that works functionally, I'm guessing the quality of the clock is going to be an issue (but I'm in the process of understanding DSD
The latest version, DAC3_10, doesn't have that header anymore. I replaced it with three U.FL connectors to reduce crosstalk. Driving four clock inputs from one output is not ideal, but should work.
There are posts on other forums that complain about the same thing
I just scanned through the documentation on the XMOS xCORE-200 used on the MCHStreamer, and it looks like there's a 25Mhz external PLL for base clocking (as mentioned previously), then on-chip dividing/multiplying to derive other clocks. Basically: external PLL->into the chip -> divide -> multiply ->divide again -> multiple dividers in parallel, then the "tiles" (cores) programatically gen the DSD clock. I get the jitters just thinking about it.
Edit: I'll still pick one up and see how it performs though, for science!
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Hi Marcel, Thank you for your comments. Would like to respond to some of the points.
Regarding doublers and Andrea's particular parts, the empirical evidence so far is that his particular clocks, doublers, and dac have been judged by human listeners as preferred to straight 22/24MHz clocks. So far I have found the same, although I'm using 11/12MHz clocks with a single doubler. Having said that, I don't think its the last word on what is best. Its only a tentative observation based on experience up to this point. And I would not say there is a lot of experience. Rather, we are very much still in early experimental territory.
More or less. There is a dual shunt regulator board. One regulator for Vref, and one for the digital circuitry on the dac board. The choice of shunt regulators was made experimentally. Some various regulators were tried and the one used now is the best that has been found so far. IMHO its likely possible to make a better one, but haven't done any work on it.
There are a couple of issues I would raise here. One is that phase noise skirts and amplitude noise skirts are shaped a bit differently, with phase noise skirts possibly extending to higher up spectral lines than is the case for amplitude noise. Please see page 15 of the attached document.
The other issue has to do with the audibility research you mentioned. May I ask how audibility was determined, was it by perceptual discrimination of distortion, discrimination of soundstage parameters, or maybe something else?
Sorry if it seemed that way. In response I would like to say that I thought I was warning people off of expecting too much. I tried to make it very clear all that is being offered is a set of boards, and there are not guarantees a diy'er is going to be able to fully optimize a final dac build. Also tried to make clear that what is being offered now only represents the present state of development. It is believed it will be possible to do better on the next round. I have also made clear that Andrea's products are not low-cost, which is not to say reasonable or unreasonable. They cost what they cost, and IMHO they are not cheap to make. Not everybody goes to JLCPCB to get the cheapest deal possible.
Also, I have responded to specific issues raised by people who haven't tried Andrea's dacs (obviously, as evidenced above). Andrea can't be here to do it himself, so to an extent I was trying to negate some suspicions raised that I don't think are on target.
Now, if people want to know if there are any conflicting findings between what the folks listening in Italy conclude and what we conclude here in Auburn, the answer is yes. Are there problems still under investigation? Yes. So far nobody has guessed right when they expressed concerns as to particular issues being most significant, is all. So I have been busy trying to respond to issues raised which IMHO and IME amount to 'barking up the wrong tree.'
If people want me to write up my own open concerns then I would be willing to do that. The purpose of this post is to respond to some issues you raised.
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I was referring to the graph I found in Brian Moore's book, see https://www.diyaudio.com/community/threads/phase-noise-in-ds-dacs.387862/post-7066124
It applies to simple three-tone complexes consisting of a carrier and two small sideband tones. At various levels of the sideband tones, it was determined whether people heard a difference between sidebands on or off.
Depending on the phase relations, the sideband tones either modulate the amplitude of the total signal, or mainly modulate the phase. At least for these tone complexes, the extra tones are at small frequency offsets more audible when they modulate the amplitude than when they modulate the phase. At larger frequency offsets, it doesn't make much difference anymore.
It applies to simple three-tone complexes consisting of a carrier and two small sideband tones. At various levels of the sideband tones, it was determined whether people heard a difference between sidebands on or off.
Depending on the phase relations, the sideband tones either modulate the amplitude of the total signal, or mainly modulate the phase. At least for these tone complexes, the extra tones are at small frequency offsets more audible when they modulate the amplitude than when they modulate the phase. At larger frequency offsets, it doesn't make much difference anymore.
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Okay. Thank you. Its one way to measure, but not the only way. Also, I always like to point out that thresholds normally refer to the 'the average ear' (i.e. the middle of the the bell curve).
The way we evaluate phase noise here is in terms of how perceptual discrimination of soundstage changes. The effects may have more to do with ITD than with frequencies combined in different phases.
The way we evaluate phase noise here is in terms of how perceptual discrimination of soundstage changes. The effects may have more to do with ITD than with frequencies combined in different phases.
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@MarcelvdG I'm looking at finding an externally clockable alternative to the MCHStreamer device, including a diy approach. Could the Tentlabs XO clock work nominally to supply the FIRDAC with a solid clock signal, assuming the appropriate pair of raw DSD streams? I'm piecing something together & wonder if I need to level adjust or buffer the signal. The XO would be in the same case, and close to the FIRDAC clock input.
In case anyone reading along would like hear a demonstration of the audible effects that can be caused by phase rotations: https://purifi-audio.com/blog/tech-notes-1/doppler-distortion-vs-imd-7
The DAC needs a bit clock, so this will only work if the bit clock is the crystal clock, which means only one DSD rate is supported.
1. The DC level with respect to ground (is that what you meant?) depends on whether the DAC outputs are connected to the filter or are open. In the latter case, about 1.24 V.
2. Quite close to 0 with the filter connected, otherwise 1.24 V peak differential at 0 dB DSD, that is, on average 75 % ones and 25 % zeros or the other way around in the signal peaks.
3. About 4.96 V (1.24 V bandgap reference amplified by a factor of four).
2. Quite close to 0 with the filter connected, otherwise 1.24 V peak differential at 0 dB DSD, that is, on average 75 % ones and 25 % zeros or the other way around in the signal peaks.
3. About 4.96 V (1.24 V bandgap reference amplified by a factor of four).