According to the scope it is at the designed frequency, the scope rounds it off to 22,5mhz, see picture. But it shifts a bit between 22,4-22,7mhz. I do not know if it is the accuracy of the scope, test leads or the way I have connected the clock to the scope.
You are right about the impedance. A test with 47ohm load looks a lot better!
Sorry for the mistake
You are right about the impedance. A test with 47ohm load looks a lot better!
Sorry for the mistake
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D
Deleted member 537459
Are you sure is correct crystal? The board is drixo, I se in the picture the crystal is tiny.
According to the scope it is at the designed frequency, the scope rounds it off to 22,5mhz, see picture. But it shifts a bit between 22,4-22,7mhz. I do not know if it is the accuracy of the scope, test leads or the way I have connected the clock to the scope.
You are right about the impedance. A test with 47ohm load looks a lot better!
Sorry for the mistake
why you left unsoldered the two caps near the voltage reference ? (aka C43-C45)
Thanks ... I had not seen.
These capacitors are mandatory, without them the voltage reference oscillates.
P.S. Took a second look at your board, and I spotted those little pesky gate inductors
. That must be it .
No, it does not sing; unlike ~HPM6.1 or what it was called it has no negative
input impedance at 100 KHz because of the delayed feedback.
The 4 parallel gate/drain lines would form an efficient resonator
at 650 MHz, and the 16 CPH3910 would be more than happy to put it
to use.
If the ferrite beads had an stability effect at 100 KHz, they would also
have a noise effect at 100 KHz.
I had FET amplifiers long before, {pic1}, Interfet IF3602 or a herd of BF862
and the Wenzel design ( from his phase noise measurement machine, pic2,
partly populated ) even 10 years earlier.
They all share the misfeature of not being unconditionally stable.
Gerhard
input impedance at 100 KHz because of the delayed feedback.
The 4 parallel gate/drain lines would form an efficient resonator
at 650 MHz, and the 16 CPH3910 would be more than happy to put it
to use.
If the ferrite beads had an stability effect at 100 KHz, they would also
have a noise effect at 100 KHz.
I had FET amplifiers long before, {pic1}, Interfet IF3602 or a herd of BF862
and the Wenzel design ( from his phase noise measurement machine, pic2,
partly populated ) even 10 years earlier.
They all share the misfeature of not being unconditionally stable.
Gerhard
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You must be joking, “delayed feedback” .
And you know that, reactances have no Johnson noise, while the input current of JFETs is virtually nil, so no noise current drop.
Glad you finally arrived to the solution I built 10 years ago, too bad you wasted time on all kind of other hopeless attempts. Your next step is to go to 64 JFETs in parallel, you’ll get at 0.15nV/rtHz like myself.
Don’t worry, I’m not asking for royalties, after all this idea was developed in the ‘60s.
.And you know that, reactances have no Johnson noise, while the input current of JFETs is virtually nil, so no noise current drop.
Glad you finally arrived to the solution I built 10 years ago, too bad you wasted time on all kind of other hopeless attempts. Your next step is to go to 64 JFETs in parallel, you’ll get at 0.15nV/rtHz like myself.
Don’t worry, I’m not asking for royalties, after all this idea was developed in the ‘60s
.
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Yes, thanks for your help! I have overlooked this in the process of building 6 of these modules, after soldering so many components I missed these. How stuped of me
I soldered the caps and now it is working!
Now another problem has arisen. The fifopi does not lock onto the clock when two of them are connected. I have the 22 and 24mhz clocks connected. I can only use one of them connected.
I sent Ian a message of this problem but he has no solution.
One note he made was that the XO output logic levels might be too low.
On the picture you can see the setup on my dddac with 22-24mhz clocks.
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Yes, thanks for your help! I have overlooked this in the process of building 6 of these modules, after soldering so many components I missed these. How stuped of me
I soldered the caps and now it is working!
Now another problem has arisen. The fifopi does not lock onto the clock when two of them are connected. I have the 22 and 24mhz clocks connected. I can only use one of them connected.
I sent Ian a message of this problem but he has no solution.
One note he made was that the XO output logic levels might be too low.
On the picture you can see the setup on my dddac with 22-24mhz clocks.
Please, put your probe at the output of the two sine to square converter when both are connected to see the output level.
The output should be a square wave from ground to around Vcc of the squarer.
I did some measurements and this shows that the q1 fifopi has issues with 2 clocks.
First 2 pictures; two clocks
Last 2 pictures; one clock
First 2 pictures; two clocks
Last 2 pictures; one clock
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Before FIFO_Pi 3, the old FIFO_Pi design used the disable pin on the clocks as needed to turn one clock off, and turn the other clock on. Since Andrea's squarers don't have a disable pin, the old FIFO_Pi clock selection system won't work with two of them. With FIFO_Pi 3, it isn't required to use the clock disable pin, there is some other means of gating which clock is enabled and which one is disabled. That means two squarers can be used.
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