Sorry to SPAM. I thought this relevant to my previous two posts.
There is USB Power from PC, but doesn't go to board.
So it looks like you can power Q3 with ConditionerPi 3.3V.
I take it you can just DC input 3.3V of both Q3 terminals if J3 needed at all?
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Found some leads this morning in the Group Buy thread, but still confused. I can play safe with 5V + 3.3V, but if there's a chance for 3.3V + 3.3V that would be lovely.
EDIT: I think I get it.
EDIT: I think I get it.
When Ian mentions both. I take it as both 5V and 3.3V off the CondtionerPi. Looks like no choice but to go 5V + 3.3V. Maybe the 5V is needed for extra USB functionality.
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A123, in the absence of others I'm willing to stick my head over the parapet...
My understanding, based on reading the manuals and my experience with FifoPi Q2 (I do not have TransportPi or ConditionerPi) is this:
- FifoPi Q3 requires 3.3v at J5 to power the clean side of the board.
- Any power being fed from J1 underneath (from RPi, ConditionerPi, other battery board, etc) is largely going to the non-isolated header of Q3 (labelled J2).
- 3.3v from this non-isolated side goes to pin 1 of the isolated header (J7), with isolated 3.3v at pins 2 and 4 coming from the isolated input J5.
- Connector J3 feeds 3.3v to the non-isolated header (J2), pin 1 of J7, and back down to preceding boards through J1 to RPi, etc - in your case you're not using an RPi so this is not used.
- Given that (according to the Q3 manual) no 5v rail is present on the isolated header (J7), TransportPi must be able to operate on just 3.3v. However: pin 18 of TransportPi's HDMI output connector J10 specifies 5V, and the GPIO table for TransportPi shows pins 2 and 4 being for 5v rails. This is the bit that is confusing me (and why it's taken me 4 tries at writing this!!).... Please review the GPIO tables of Q3 and TransportPi - I feel that this is the point that needs clarifying to understand your powering needs, and decide whether ConditionerPi is an ideal solution for you. Can anyone else confirm or shoot this down?
IF I'm understanding correctly, you could use ConditionerPi, feeding the 5v output to the alternative 5v input of TransportPi and the 3.3v LDO output (min 150mA) to the Q3.
However, according to my reading of the ConditionerPi manual - Specification on P.1, gpio table on P.5 - only the 5v supply is conditioned (utilizes the uC's), whereas the 3.3v output is "merely" filtered. So this may not give you optimum conditioned power to Q3...
Clear as mud. Clarity is finding the Right speck of mud...
Kind regards, Simon
My understanding, based on reading the manuals and my experience with FifoPi Q2 (I do not have TransportPi or ConditionerPi) is this:
- FifoPi Q3 requires 3.3v at J5 to power the clean side of the board.
- Any power being fed from J1 underneath (from RPi, ConditionerPi, other battery board, etc) is largely going to the non-isolated header of Q3 (labelled J2).
- 3.3v from this non-isolated side goes to pin 1 of the isolated header (J7), with isolated 3.3v at pins 2 and 4 coming from the isolated input J5.
- Connector J3 feeds 3.3v to the non-isolated header (J2), pin 1 of J7, and back down to preceding boards through J1 to RPi, etc - in your case you're not using an RPi so this is not used.
- Given that (according to the Q3 manual) no 5v rail is present on the isolated header (J7), TransportPi must be able to operate on just 3.3v. However: pin 18 of TransportPi's HDMI output connector J10 specifies 5V, and the GPIO table for TransportPi shows pins 2 and 4 being for 5v rails. This is the bit that is confusing me (and why it's taken me 4 tries at writing this!!).... Please review the GPIO tables of Q3 and TransportPi - I feel that this is the point that needs clarifying to understand your powering needs, and decide whether ConditionerPi is an ideal solution for you. Can anyone else confirm or shoot this down?
IF I'm understanding correctly, you could use ConditionerPi, feeding the 5v output to the alternative 5v input of TransportPi and the 3.3v LDO output (min 150mA) to the Q3.
However, according to my reading of the ConditionerPi manual - Specification on P.1, gpio table on P.5 - only the 5v supply is conditioned (utilizes the uC's), whereas the 3.3v output is "merely" filtered. So this may not give you optimum conditioned power to Q3...
Clear as mud. Clarity is finding the Right speck of mud...
Kind regards, Simon
Thanks for going out on a limb...
No rush on this. This is for my secondary system for the second half of the year, so it is just planning phase.
My goal is to try to avoid using 5V on the MKIII. The ConditonerPi is not on the radar at all, it was just used as a example of the 3.3V possibility. The Uc Hybrid is a more robust solution than ConditionerPi. I had always assumed that the 5V on the MKIII was battery-powered. I even have a UC Mate 5V allocated for this purpose. I just figured it out recently that 5V is not battery-powered as I was preparing to implement the MKIII soon for temp StationPi build not permanent BridgePi build. I was like wait, 2 X 3.3V + 4 X 3.3V for 13.2V + 4 X 3.3V for 13.2V; where is the 5V? Oh, it's a LPS on the 5V. I have been spoiled since I get 5V battery power on my BMS, so overlooked researching the MKIII 5V.
So since I'm moving away from StationPi to focus on BridgePi, the possibility of eliminating the need for 5V has presented itself. Especially since it's RPi-less.
For the StationPi to power the Q3, you only need 3.3V on StationPi J5. So over time, I just hope to get a similar confirmation for the BridgePi. No need to dig down and investigate the schematic as it's a future project and we can probably get a confirmation in time. Similar to StationPi 3.3V when we were all speculating on 3.3V until we got the sign off.
At first, it didn't seem possible for StationPi to utilise 3.3V:
But then:
So now it's official FiFoPi Q3 can be powered via 3.3V on StationPi J5. I'm just hoping to get a similar official statement this is possible on the BridgePi build. But USB (5V) is involved on the BridgePi, so it may not be. Plus the sample size of users on BridgePi is lower than StationPi so harder to confirm.
BridgePi << No Power Needed since NO RPi >>
Amanero << 5V USB power from PC, but cuts off from going to board >>
FiFoPi Q3 << 5V, but maybe 3.3V is good to go similar to StationPi J5? >>
TransportPi << 3.3V via GPIO or independent 3.3V power, not an issue >>
I will be extremely happy if 5V is not needed as this will be a super clean BridgePi build if it is all 3.3V SuperCapped. It would be a dream and makes justifying going BridgePi instead of a 2nd StationPi build the right play.
No rush on this. This is for my secondary system for the second half of the year, so it is just planning phase.
My goal is to try to avoid using 5V on the MKIII. The ConditonerPi is not on the radar at all, it was just used as a example of the 3.3V possibility. The Uc Hybrid is a more robust solution than ConditionerPi. I had always assumed that the 5V on the MKIII was battery-powered. I even have a UC Mate 5V allocated for this purpose. I just figured it out recently that 5V is not battery-powered as I was preparing to implement the MKIII soon for temp StationPi build not permanent BridgePi build. I was like wait, 2 X 3.3V + 4 X 3.3V for 13.2V + 4 X 3.3V for 13.2V; where is the 5V? Oh, it's a LPS on the 5V. I have been spoiled since I get 5V battery power on my BMS, so overlooked researching the MKIII 5V.
So since I'm moving away from StationPi to focus on BridgePi, the possibility of eliminating the need for 5V has presented itself. Especially since it's RPi-less.
For the StationPi to power the Q3, you only need 3.3V on StationPi J5. So over time, I just hope to get a similar confirmation for the BridgePi. No need to dig down and investigate the schematic as it's a future project and we can probably get a confirmation in time. Similar to StationPi 3.3V when we were all speculating on 3.3V until we got the sign off.
At first, it didn't seem possible for StationPi to utilise 3.3V:
But then:
So now it's official FiFoPi Q3 can be powered via 3.3V on StationPi J5. I'm just hoping to get a similar official statement this is possible on the BridgePi build. But USB (5V) is involved on the BridgePi, so it may not be. Plus the sample size of users on BridgePi is lower than StationPi so harder to confirm.
BridgePi << No Power Needed since NO RPi >>
Amanero << 5V USB power from PC, but cuts off from going to board >>
FiFoPi Q3 << 5V, but maybe 3.3V is good to go similar to StationPi J5? >>
TransportPi << 3.3V via GPIO or independent 3.3V power, not an issue >>
I will be extremely happy if 5V is not needed as this will be a super clean BridgePi build if it is all 3.3V SuperCapped. It would be a dream and makes justifying going BridgePi instead of a 2nd StationPi build the right play.
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Sorry A123, I took it that you may have already had the ConditionerPi
Could you possibly give me the post number from the second quote in your response? I'd like to check context to develop my understanding of what's happening, esp in conjunction of the FPGA requirements (I need to know how Everything works - consequently I don't have time to work out how Anything works!!). I would have thought the StationPi J5 power requirement would then depend if you are utilizing fifo and signal re-clocking, or just providing a clock source for the TransportPi - so I need to do some more reading.
I'm also looking at BridgePi in a later part of the build for USB to I2S as an extra input rather than main input (which will be RPi or USBridge Sig depending on finances/ connection to reality); but I hear you on the hopefully simplified power routing - I wish RPi didn't need 5v as well!
Regards.
Could you possibly give me the post number from the second quote in your response? I'd like to check context to develop my understanding of what's happening, esp in conjunction of the FPGA requirements (I need to know how Everything works - consequently I don't have time to work out how Anything works!!). I would have thought the StationPi J5 power requirement would then depend if you are utilizing fifo and signal re-clocking, or just providing a clock source for the TransportPi - so I need to do some more reading.
I'm also looking at BridgePi in a later part of the build for USB to I2S as an extra input rather than main input (which will be RPi or USBridge Sig depending on finances/ connection to reality); but I hear you on the hopefully simplified power routing - I wish RPi didn't need 5v as well!
Regards.
^^
No worries. I doubt anyone of us know one another's Ian gear intimately. I brought up ConditionerPi, so it makes sense to deduce I may have a one.
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
I'm barely back to getting into the mindset of Ian's LiFePO4 solutions. After this week, I should be finally moved on from my previous portable project which I was using a third-party BMS. So I will start researching all this all over again and try to refresh my memory.
With StationPi, the RPi 5V is sort of out of the loop and the FiFoPi runs isolated as full on clean 3.3V solution. So I guess that makes me happy even though 5V in the chain. With the ReclockPi which replaces the ShieldPi to offer RFI/EMI protection on top will make things even better.
Yes, I think if BridgePi can be full on 3.3V it's an attractive solution. Crossing fingers. I may have to reconsider a 2nd StationPi now if BridgePi is 5V. I didn't think too much about the StationPi being a complete isolated 3.3V until now so it's a good backup plan.
No worries. I doubt anyone of us know one another's Ian gear intimately. I brought up ConditionerPi, so it makes sense to deduce I may have a one.
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
I'm barely back to getting into the mindset of Ian's LiFePO4 solutions. After this week, I should be finally moved on from my previous portable project which I was using a third-party BMS. So I will start researching all this all over again and try to refresh my memory.
With StationPi, the RPi 5V is sort of out of the loop and the FiFoPi runs isolated as full on clean 3.3V solution. So I guess that makes me happy even though 5V in the chain. With the ReclockPi which replaces the ShieldPi to offer RFI/EMI protection on top will make things even better.
Yes, I think if BridgePi can be full on 3.3V it's an attractive solution. Crossing fingers. I may have to reconsider a 2nd StationPi now if BridgePi is 5V. I didn't think too much about the StationPi being a complete isolated 3.3V until now so it's a good backup plan.
Just focus on your studies. I think we will eventually get a confirmation over time.
Also, I think I'm going to postpone any new BridgePi or StationPi purchases since I'm way over-budget DIYing (too many unplanned Mouser / Digikey receipts) for this year. Any new BridgePi or StationPi will also require another duplicate FiFoPi Q3, TransportPi, RPi and ReclockPi. It's better optimally to postpone also if new revisions are released, for example TransportPi II, etc. versus just duplicating the effort.
So I'm just going to focus on optimising my current StationPi and make it modular. This will allow me to easily swap between desktop and transportable systems. I'll just replace the terminals with these:
Having this discussion has made me appreciate the StationPi more since I can live with 5V if the 3.3V clean side is isolated. I guess I just needed to refresh my memory.
I think there's some hope for the BridgePi:
There's a big "or 3.3V". I think this relates to FiFoPi and not TransportPi.
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Also, I think I'm going to postpone any new BridgePi or StationPi purchases since I'm way over-budget DIYing (too many unplanned Mouser / Digikey receipts) for this year. Any new BridgePi or StationPi will also require another duplicate FiFoPi Q3, TransportPi, RPi and ReclockPi. It's better optimally to postpone also if new revisions are released, for example TransportPi II, etc. versus just duplicating the effort.
So I'm just going to focus on optimising my current StationPi and make it modular. This will allow me to easily swap between desktop and transportable systems. I'll just replace the terminals with these:
Having this discussion has made me appreciate the StationPi more since I can live with 5V if the 3.3V clean side is isolated. I guess I just needed to refresh my memory.
I think there's some hope for the BridgePi:
There's a big "or 3.3V". I think this relates to FiFoPi and not TransportPi.
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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I think I remembered skim reading somewhere that the StationPi only passes the I2S data from RPi to FiFoPi, so 5V not needed and isolated.
This might hold true too for the BridgePi if it just passes I2S data. 5V may not be needed, isolated.
So all the other GPIO pins are not relevant, just the I2S pins are passed through.
Could be completely wrong, just late night skim reading...
This might hold true too for the BridgePi if it just passes I2S data. 5V may not be needed, isolated.
So all the other GPIO pins are not relevant, just the I2S pins are passed through.
Could be completely wrong, just late night skim reading...
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pinch / grain of salt everyone... don't flame me.
speculative price range on rumored Accusilicon 338. ouchie.
translated from a Chinese forum:
speculative price range on rumored Accusilicon 338. ouchie.
translated from a Chinese forum:
Good time to save some of dem Renminbi if launched in 2021. Fortunately I just need a clock for Redbook. Can't justify two clocks @ USD700. Maybe. Brutal hobby.
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Nice work Ian.
Your youtube video is very good at explain how all "legos" shoud be stack together.
Just one thing. Although perfection why you still didn"t replaced capacitors under Fifopi. If you stack Fifopi on ReceiverPi, capacitors stuck on spdif transformer. This was with last fifo and this new fifo.
Whay is on Station pi dirty gnd pin that should be connect to isolated clean side gnd of Fifopi?
Your youtube video is very good at explain how all "legos" shoud be stack together.
Just one thing. Although perfection why you still didn"t replaced capacitors under Fifopi. If you stack Fifopi on ReceiverPi, capacitors stuck on spdif transformer. This was with last fifo and this new fifo.
Whay is on Station pi dirty gnd pin that should be connect to isolated clean side gnd of Fifopi?
$50 for AS338
I was quoted $50 US per clock via email by Acculisicon for the AS338.
Via email from their rep....echoing prior shared info, I realize. I asked where to purchase in reply but they haven't replied back yet.
"
All of AS338 tested performance but close-in (tyipcal 0.1Hz - 10Hz) phase noise still some deviation,
through the trial-produce test result distribution pertty okay. I have to say something about "Listening",
AS338 is not just "AS318B update", it is totally new thing - optimized sound quality first, new sealed
case and hi-end quality inverted-mesa AT-Cut crystal and almost lowest noise oscillation ASIC, then
we got low phase noise and good short-term stability spec. In fact ACCUSILICON is semiconductor
company that's why we can make so low jitter oscillators line, Most audiophile feel OCXO sound better
than SPXO one of key reason is OCXO short-term stability much much much better than SPXO, so we
improve this in AS338 design, alothugh AS388 still worse than high-quality OCXO, it is cost issue lah.
By the way ACCUSILICON also provide high quality OCXO products :]
AS338 only provide 45M1584/49M152, and so plan 22M5792/24M576, some of customers told us higer
frequency is future, include XMOS system. maybe you can waiting for our new clock divider chip 2021Q3
change 45M1584/49M152 to 22M5792/24M576 without performance degradation, but I still recommend
you can use 45M1584/49M152 directly.
I suggestion through international trader for lower shipping cost. We will consider how to
get them easy in North America."
I was quoted $50 US per clock via email by Acculisicon for the AS338.
Via email from their rep....echoing prior shared info, I realize. I asked where to purchase in reply but they haven't replied back yet.
"
All of AS338 tested performance but close-in (tyipcal 0.1Hz - 10Hz) phase noise still some deviation,
through the trial-produce test result distribution pertty okay. I have to say something about "Listening",
AS338 is not just "AS318B update", it is totally new thing - optimized sound quality first, new sealed
case and hi-end quality inverted-mesa AT-Cut crystal and almost lowest noise oscillation ASIC, then
we got low phase noise and good short-term stability spec. In fact ACCUSILICON is semiconductor
company that's why we can make so low jitter oscillators line, Most audiophile feel OCXO sound better
than SPXO one of key reason is OCXO short-term stability much much much better than SPXO, so we
improve this in AS338 design, alothugh AS388 still worse than high-quality OCXO, it is cost issue lah.
By the way ACCUSILICON also provide high quality OCXO products :]
AS338 only provide 45M1584/49M152, and so plan 22M5792/24M576, some of customers told us higer
frequency is future, include XMOS system. maybe you can waiting for our new clock divider chip 2021Q3
change 45M1584/49M152 to 22M5792/24M576 without performance degradation, but I still recommend
you can use 45M1584/49M152 directly.
I suggestion through international trader for lower shipping cost. We will consider how to
get them easy in North America."
That would be very reasonable if it's around $50.
I read that the AS338 is suppose to compete in the SOTA category so it's not a direct upgrade to the AS318 (Hi-Fi Category). Audiophonics has such a high markup so pricing can be deceiving.
This would be a great alternative to the "Pulsar" clocks as procuring from Russia is not exactly straightforward process.
I read that the AS338 is suppose to compete in the SOTA category so it's not a direct upgrade to the AS318 (Hi-Fi Category). Audiophonics has such a high markup so pricing can be deceiving.
This would be a great alternative to the "Pulsar" clocks as procuring from Russia is not exactly straightforward process.
Okay, I'm in between projects so feeling refreshed now to tackle the MKIII.
I bought too high of power soldering iron so returned it and have a 80W soldering iron on the way.
Since I fried my BMS, I have no way to charge the A123 26650 before I startup the MKIII.
In the manual it mentions as long as all the batteries are within 5% voltage of one another should work too.
My 26650 are all in one sealed plastic package from the factory. I'm thinking it's okay since they should all be within the 5% range. Is it recommended to fully charge each battery before MKIII first use?
I am in no rush so can order another BMS to charge up the 26650 if needed before first use.
I bought too high of power soldering iron so returned it and have a 80W soldering iron on the way.
Since I fried my BMS, I have no way to charge the A123 26650 before I startup the MKIII.
In the manual it mentions as long as all the batteries are within 5% voltage of one another should work too.
My 26650 are all in one sealed plastic package from the factory. I'm thinking it's okay since they should all be within the 5% range. Is it recommended to fully charge each battery before MKIII first use?
I am in no rush so can order another BMS to charge up the 26650 if needed before first use.
I'm not too experienced in clocks to determine what is or what isn't SOTA. It maybe just a way to distinguish the high performance clocks from the average performance clocks.
From what I skimmed on the clock threads, I know Andrea classifies his clocks as SOTA. The only other clock that maybe worthy of SOTA is Pulsar. Almost forgot about Neutron. Neutron as well.
If the Accusilicon AS338 can get close to the "SOTA" performance range, that would be a great boon for this hobby. Especially with a small footprint and reasonable price.
From what I skimmed on the clock threads, I know Andrea classifies his clocks as SOTA. The only other clock that maybe worthy of SOTA is Pulsar. Almost forgot about Neutron. Neutron as well.
If the Accusilicon AS338 can get close to the "SOTA" performance range, that would be a great boon for this hobby. Especially with a small footprint and reasonable price.