The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator

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The performance of the latest circuit is exemplary. Almost too good. I would want to cross check the instrument (timepod?) with a known source just to be sure its accurate. There is a note on Wenzel's site about doing just that.

1/F noise in the amplifier is the main limit to close in phase noise if everything else is right.

Very interesting design from the two academics. Following on from that I believe it would be possible to use an ultralow noise audio opamp as the active element in a crystal oscillator. Most would have enough gain at 5 or 10 MHz to work and using a transformer at the input to get the best noise matching is a great idea.
 
Andrea, you are to be commended on this effort, amazing results.

You've managed to extract not only extremely low phase noise close to carrier but also a very low phase noise floor. WRT the latter, this may not
seem that important but once we start multiplying to get 22 or even 45 M, on traditional designs that have sacrificed noise floor to obtain extremely low
close in phase noise then the NF will rise considerably after multiplying.

Recently I have become aware of a new super low phase noise 10 MHz Ref OCXO design by some people at the University of York. This design achieves
the following phase noise specs:
1Hz, -123dBc, 10Hz, -148dBc, 100Hz, -157dBc, 1k, -161dBc etc.
The Allan Dev is <2x10^-13 / 1 sec

Given that for the lowest possible phase noise, especially close to carrier, 5MHz is optimum, then the 'York' OCXO design is *possibly slightly better
but it's a very close call and we must also consider that this design is a collaborative effort by experts in the field. Link to white paper and
full schematic below.

http://eprints.whiterose.ac.uk/141563/1/08540461.pdf

Of interest to note, the 'York' uses a unique transformer coupled, differential OP design with the active device being an SSM2212 low noise 'audio type'
transistor as opposed to the usual RF BJT. One characteristic the SSM device does have is among the lowest 1/f noise for any device I'm aware of being
sub 1Hz. Most RF designers probably wouldn't consider using such a device however the Ft is 300MHz with enough current the high Cob is not such a
problem at 5 to 10MHz and low circuit impedances. Exactly how much the active device 1/f noise translates to close in phase noise, I'm not sure,
hopefully others here can clarify but the white paper alludes to some importance.

Count me in when you do the GB.

PS - If you need any help with a suitable enclosure or mounting let me know, I've got many yrs 2d/3d CAD modelling under the belt.

TCD

Hi Terry,

just do it, the second oscillator we are testing is just the York design with some variations. The new Driscoll is ready, while we are optimizing the York type. The original circuit has higher broadband noise against the Driscoll and also the output level is too low, so we are working solve these issues.

The prototype board of the modified York is on the way, time for final tuning.
 
The performance of the latest circuit is exemplary. Almost too good. I would want to cross check the instrument (timepod?) with a known source just to be sure its accurate. There is a note on Wenzel's site about doing just that.

1/F noise in the amplifier is the main limit to close in phase noise if everything else is right.

Very interesting design from the two academics. Following on from that I believe it would be possible to use an ultralow noise audio opamp as the active element in a crystal oscillator. Most would have enough gain at 5 or 10 MHz to work and using a transformer at the input to get the best noise matching is a great idea.

Hi Demian,

Yes, the gear is the Timepod and we are sure it performs accurate measurements since we have compared the phase noise plots of a pair of known OCXO that was measured using the Aeroflex PN900 and the Agilent E5052A. The plots are identical.

From the many tests we have done in the last months we have observed that the close-in phase noise (below 10 Hz) is not affected much by the active device, the New Driscoll uses an ordinary 3904.
In the region below 10Hz from the carrier the phase noise is hevily affected by the flicker noise of the crystal.
 
That fits the photos I have stolen from Rubiola's book and placed at Jocko's
< DIYHiFi.org • View topic - To clock or not to clock, that is the question... >

Methinks the York design could be even better. They only get an operating
Q of 490K from 1.39 Meg unloaded . Part of it could come from the fact that
the crystal is driven from a +- 50-Ohm source, and the impedance at the
input side of the step up transformer is also not 0. With a crystal R0 = 53 ohm
most resonance losses thus happen outside of the resonator.

Tomorrow I'll get a board for a folded cascode Driscoll that fits the
Morion 5 MHz SC crystal. :) Runs on +-5V.

Cheers, Gerhard

BTW I've not yet implanted the replacement attenuators, should happen
really soon now.
 
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Hi guys, perhaps someone here can help me out. I’m thinking of using a fan out buffer like the lmk1c11x and normally I wouldn’t give a damn about the added 7,5fs of rms jitter but with the awesome jitter values Andrea gets with the new clock design it means almost doubling the jitter.
So in short: Do you think I can neglect the jitter added by such a buffer or should I try to avoid them and compensate by a more complicated pcb design?
Any suggestions are welcome ^^

Greetings Oli
 
Hi Terry,

just do it, the second oscillator we are testing is just the York design with some variations. The new Driscoll is ready, while we are optimizing the York type. The original circuit has higher broadband noise against the Driscoll and also the output level is too low, so we are working solve these issues.

The prototype board of the modified York is on the way, time for final tuning.

This is awesome, I made 6 pcb's accomodating the York design already and curious if your modifications would fit on the pcb. I also found the same amplitude problem. Not sure how to proceed, monolithic or ic and how this fits comparing measurements of the paper vs yours. Hard to amplify low levels RF without paying with LF noise..

Can't wait
 
Hi guys, perhaps someone here can help me out. I’m thinking of using a fan out buffer like the lmk1c11x and normally I wouldn’t give a damn about the added 7,5fs of rms jitter but with the awesome jitter values Andrea gets with the new clock design it means almost doubling the jitter.
So in short: Do you think I can neglect the jitter added by such a buffer or should I try to avoid them and compensate by a more complicated pcb design?

All those clock buffer chips are for telecom applications and they completely ignore the
noise outside 12KHz-20MHz to arrive at their wonderful specs. That standard is
completely OK for telecom apps, but neglecting the entire 1/f region below 12 KHz
is not what we really want.

The chips may be OK, but that must be verified.
 
I see, thanks. Was so happy to find a buffer with such low jitter values but I guess it was too good to be true :( looking at the phase noise diagrams of the chips I found until now and it seems they add a lot(!) more jitter if one includes the lower frequency domain, so I guess I’ll try to ditch the fan out buffer and so I don’t ruin all the work that went into those clocks ^^
 
I see, thanks. Was so happy to find a buffer with such low jitter values but I guess it was too good to be true :( looking at the phase noise diagrams of the chips I found until now and it seems they add a lot(!) more jitter if one includes the lower frequency domain, so I guess I’ll try to ditch the fan out buffer and so I don’t ruin all the work that went into those clocks ^^

An LTC6957 might be better suited, if you want to be flexible and want to use an IC.
 
Hi Terry,

just do it, the second oscillator we are testing is just the York design with some variations. The new Driscoll is ready, while we are optimizing the York type. The original circuit has higher broadband noise against the Driscoll and also the output level is too low, so we are working solve these issues.

The prototype board of the modified York is on the way, time for final tuning.

More to discuss later, just a quick note - to set things straight, it's worth
noting the terms of use of this design.

From page 1 of the 'York' white paper:

"Reuse
This article is distributed under the terms of the Creative Commons Attribution (CC BY) licence. This licence
allows you to distribute, remix, tweak, and build upon the work, even commercially, as long as you credit the
authors for the original work. More information and the full terms of the licence here:"
About The Licenses - Creative Commons

Not trying to rain on the parade but the original designer(s) should be respected.

TCD
 
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Hi All,

So ... just a couple of days of vacation and suddenly there are so many remarkable news in this thread. Andrea - it looks to be outstanding and I feel like quoting mterbekke here with his comment "can't wait", and again, many thanks for doing this work ;) ...

I am thinking that alongside battery supply these oscillators may be the most positive transformative contribution to a/my audio system I will ever have heard ....

@Hifoli:

Hi guys, perhaps someone here can help me out. I’m thinking of using a fan out buffer like the lmk1c11x and normally I wouldn’t give a damn about the added 7,5fs of rms jitter but with the awesome jitter values Andrea gets with the new clock design it means almost doubling the jitter.

Depending on how many outputs you need another diyaudio member (JohnW) in one of the other threads (can't remember which one, sorry) mentions that he has measured some/the best phase noise/jitter values with OnSemi's tinylogic. And in the tinylogic UHS series there's a dual buffer:

NC7WZ16

Cheers,

Jesper
 
Depending on how many outputs you need another diyaudio member (JohnW) in one of the other threads (can't remember which one, sorry) mentions that he has measured some/the best phase noise/jitter values with OnSemi's tinylogic. And in the tinylogic UHS series there's a dual buffer:

NC7WZ16

Cheers,

Jesper

Jesper,

Good old 74ACxxx logic at 5 V has the lowest phasenoise I've measured - Tinylogic has higher Phasenoise - a second issue with tinylogic is its edge control circuitry which gives 3 defined output drive levels during the switching edge...

I still use Tinylogic due to its lower package impedancies and no inherent Gate crosstalk - however I parallel Gates where possible to reduce there noise contribution and increase drive current.
 
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Joined 2006
References?

You can evaluate yourself the performance of the new oscillator with a simple comparison.
In your OP (post #1), you vaguely referenced Jocks orig. "low-noise" regulator when he himself professed to having lifted from some ham radio book.
Just curious ... about the various designs in this thread ... what were the some references you drew from? E.g., university or college textbook, electronics magazine, Elektor, web sites , etc.
 
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Jesper,

Good old 74ACxxx logic at 5 V has the lowest phasenoise I've measured - Tinylogic has higher Phasenoise - a second issue with tinylogic is its edge control circuitry which gives 3 defined output drive levels during the switching edge...

I still use Tinylogic due to its lower package impedancies and no inherent Gate crosstalk - however I parallel Gates where possible to reduce there noise contribution and increase drive current.

Hi John ... & thanks for clarifying. Remarkable that such "venerable" 74AC logic is still very good in some respects by today's standards ...

Cheers,

Jesper
 
In your OP (post #1), you vaguely referenced Jocks orig. "low-noise" regulator when he himself professed to having lifted from some ham radio book.
Just curious ... about the various designs in this thread ... what were the some references you drew from? E.g., university or college textbook, electronics magazine, Elektor, web sites , etc.

You can find tons of documents on the web about Clapp (1948), Pierce (1938) and Driscoll (1973) oscillators ("the various designs in this thread").
Simply do a Google search, you will found several interesting documents explaining how the above oscillators work.

Moreover, do a Google search about "oscillator phase noise". Again you will find tons of documents explaining the impact of phase noise in oscillator quality, then you can compare yourself the various plots published in this thread.

Sorry but I have no time to do it for you.
 
Jesper,

Good old 74ACxxx logic at 5 V has the lowest phasenoise I've measured - Tinylogic has higher Phasenoise - a second issue with tinylogic is its edge control circuitry which gives 3 defined output drive levels during the switching edge...

I still use Tinylogic due to its lower package impedancies and no inherent Gate crosstalk - however I parallel Gates where possible to reduce there noise contribution and increase drive current.

Hey thanks, that's a nice tip, I'll try it without buffers and try to make it up by proper routing/termination, I guess it will come to down to the amount of reflection that I'll get. Only problem I have is that with the output resistance of the driver I'm dealing with, the calculation for source termination of parallel transmission lines (Rsource = Z0 -Rdriver*N , N = Number of parallel transmission lines) gets negative so there is no Rsource I can set to completely eliminate Reflections so I just will put in 22Ohms and see how well that works out.
If it won't work that way I now have a plan B and I'll go with 74ac... in parallel :yes:
greetings Oli
 
I'm not sure if KHashmi316 is a troll but sure as hell he's amusing, I leave this here ;D

Say, I have a Philips CD player with SAA7220 and TDA1541A, and I want to upgrade the clock.
PRICE NO OBJECT. EFFORT NO OBJECT.
I would choose ST cut Laptec 11.289 Mhz. But which TWTMC circuit should I opt for:
TWTMC-D
TWTMC-C
TWTMC-P

--
Sorry, but it ain't worth my time to search for messages the OLD FASHIONED WAY.
If you want to impress, try using hyperlinks.
PSSSSSTT: That's why the Internet was invented ;)
 
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