Just reading the specs on the chips for this.
I see the CT chip provides a pass through clock ref but also a I2S clock output
The I2S clock is at rate of the source (ie upto 512K DSD at 8x)
The shift registers are all tied together by the I2S clock output
Therefore the switching is occurring at the I2S rate and no shift register clock upsampling.
So I assume any digital switching noise at the shift register changes into the resistor network is at the I2S rate in the output feed into the output stage?
I see the CT chip provides a pass through clock ref but also a I2S clock output
The I2S clock is at rate of the source (ie upto 512K DSD at 8x)
The shift registers are all tied together by the I2S clock output
Therefore the switching is occurring at the I2S rate and no shift register clock upsampling.
So I assume any digital switching noise at the shift register changes into the resistor network is at the I2S rate in the output feed into the output stage?
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It's connected to the DSD_0_SCLK_OUT pin on the chip.
Ok, so if the R network (I note that it's not R2R) is driven in a similar style as the LPCM. LPCM providing the absolute voltage level in the word - that being shifted into registers (LSB-MSB) and clocked onto the resistor network.
Most LPCM are upsampled so that the R2R network is driven at a rate 2.8-3.2MHz to overcome switching noise. This can be done by simply FFTing, zero padding and inverse FFT on the fly. With LPCM the MSB resistor tolerances are very important to not affect the LSB resistors.
A DSD just is slightly different in the format of the sample word (recorded), assuming fully native and the output IS DSD (rather than LPCM) then the resistor network simply provides the values based on the width of bit 1 DSD encoded bits. As each resistor is approximately equal (for a linear step) then the tolerance is simply the same, thus a 0.001% would be needed for all the resistors or an uneven output would occur.
Just assuming you're doing the latter - native DSD onto the resistor network?
The reason I ask is that the shift registers have varing voltages as a consequence of the resistors on each pin, however a 5V output would override all the other bits as they’re all connected to the same rail. This would cause a problem with native DSD output driving the resistor network.
I’m just trying to understand how a 32 resistor network supports 2^32 voltage levels when the outputs are all tied together without a R2R network - only way I can see this working is tying the voltage to the discharge rate of the capacitor on exit.
Using a cap decay design means the tolerance (temp/age) is then in the output cap.
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Ahh... or the ladder is being used as a voltage divider (all outputs to the same line) between the 5V and 0V (using a 1 bit as a 5V and a 0 being 0V). However this would be a complex bit pattern to balance the 0V and 5V for each of the 2^32 bit values however using a back prop network it would be easy to find a way to find resistor values that can synthesise values using both +5V, 0 and -5V.
Maybe I'll try creating a octave program to see if this is possible.
Maybe I'll try creating a octave program to see if this is possible.
If it's a equal resistor network, then the voltage divider will be linear with 30 steps +ve over 30 steps -ve for the full range (360 steps rather than 2^31). So I'm still trying to understand how that works as native "pure" DSD and a straight R-ladder and still gives a good resolution.
Any one?
Ahh so this using a DSD moving average sine wave? The resistors encode 90 degrees of movement over 31 resistors. As a resistor ladder, with balanced ladders, this supports bots sides of the sine wave, and as a voltage divider (if both sides are used simultaneously) this can increase the resolution further. Using additional ladders allows further precision.
The tolerance of resistors has to very closely matched to ensure correctness.
Any one?
Ahh so this using a DSD moving average sine wave? The resistors encode 90 degrees of movement over 31 resistors. As a resistor ladder, with balanced ladders, this supports bots sides of the sine wave, and as a voltage divider (if both sides are used simultaneously) this can increase the resolution further. Using additional ladders allows further precision.
The tolerance of resistors has to very closely matched to ensure correctness.
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Resistors.
There are two brands & models that I will say qualify for high precision without moving over to Foil resistors and that is Panasonic ERA 10-50 ppm/K and Susumu RG which delivers 5 ppm/K (depending on value) thin film resistors.
So replacing the Vishay MMA0204 is one of the first thing I would do
The stock resistors are Vishay MMA0204 -1206, they are ± 50 ppm/K; ± 25 ppm/K but they have Thick Film noise figures - so not a great choice for high precision.
There are two brands & models that I will say qualify for high precision without moving over to Foil resistors and that is Panasonic ERA 10-50 ppm/K and Susumu RG which delivers 5 ppm/K (depending on value) thin film resistors.
So replacing the Vishay MMA0204 is one of the first thing I would do
The stock resistors are Vishay MMA0204 -1206, they are ± 50 ppm/K; ± 25 ppm/K but they have Thick Film noise figures - so not a great choice for high precision.
There are two brands & models that I will say qualify for high precision without moving over to Foil resistors and that is Panasonic ERA 10-50 ppm/K and Susumu RG which delivers 5 ppm/K (depending on value) thin film resistors.
So replacing the Vishay MMA0204 is one of the first thing I would do
AFAIK the tolerances are not that important for distortion in this design.
It's a mixed-signal FIR filter, not a multibit DAC. In principle, a single tap with a low-pass filter is all you need to convert a sigma-delta modulate (such as DSD) into analogue form. Using several taps and a shift register just reduces the effects of clock jitter. Resistor tolerances just change the weight of the FIR taps and thereby the stopband rejection, they don't cause distortion like they would in a multibit design.
See Heinrich Pfeifer, Werner Reich and Ulrich Theus, Circuit arrangements for averaging signals during pulse-density D/A or A/D conversion, US patent 4947171, 7 August 1990. If you can read Pascal, this post may also be of use: https://www.diyaudio.com/forums/dig...-sigma-delta-dac-operation-3.html#post5189375
Voltages are presented by the resistors and averaged by setting multiple bits allowing intermediate voltages.
Those resistors are the only thing that is modulating the power supply into the audio waveform. So to me the precision for resistors to the required value is important otherwise your steps will not be correct (especially with -ve on a separate bank resulting in non linearity distortion).
The reason I suspect the DSD decode is “less fussy“ is the smaller steps and no one resistor has such a large contribution. The LPCM r2r will less tolerant of the resistors as each big resistor doubles in resistance (2^n).
I would look at 0.001% SMT.
Those resistors are the only thing that is modulating the power supply into the audio waveform. So to me the precision for resistors to the required value is important otherwise your steps will not be correct (especially with -ve on a separate bank resulting in non linearity distortion).
The reason I suspect the DSD decode is “less fussy“ is the smaller steps and no one resistor has such a large contribution. The LPCM r2r will less tolerant of the resistors as each big resistor doubles in resistance (2^n).
I would look at 0.001% SMT.
Yeah I was wondering why the use of multiple resistors given the definition Of DSD is simply a 5v or 0v.
I can read pascal
I see you use a linear interpolation, you could make a better option using FFT then pad during IFFT..
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A good option Vishay NOMCT16035001AT1So replacing the Vishay MMA0204 is one of the first thing I would do
Please see my reply and read the attached PDF. You can also watch the attached YT video. There is also cost aspects and Panasonic come out on top - after that, one would look at foil resistors.
Boston AES | "Best Resistors for Audio" | Brewster LaMacchia
Yeah I was wondering why the use of multiple resistors given the definition Of DSD is simply a 5v or 0v.
I can read pascal
I see you use a linear interpolation, you could make a better option using FFT then pad during IFFT..
The Pascal program was just meant to test a hypothesis, so I didn't bother making a good interpolation filter. I have a Verilog version with good filters running on an FPGA, though, see https://linearaudio.net/sites/linearaudio.net/files/ThevalveDAC_PCB_FPGA_files for web posting.zip and https://linearaudio.net/sites/linearaudio.net/files/additionaldatavalveDACversion2p1.zip
I see the mechanism looking at the circuit diagram - the stream of single bit DSD is placed into the front of the shift register chain, the clock then moves this along the chain, making space for the next value. The 31 bits are then averaged.
This would typically have the same value resistors down the chain. The variation of values implements a filter.
This would typically have the same value resistors down the chain. The variation of values implements a filter.
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That is why the value of each resistor is not that important. Everything, including (small) variation in resistor values are averaged out. Not at all the same as in a R2R chain IMHO
I suggest you search 'moving average filter'.
The resistor values do not affect distortion. Modulation of the resistor value due to voltage swing or temperature can introduce distortion.
OP voltage swing by not driving the network into a virtual ground will also
introduce distortion.
Also finite rise / fall times of switching logic will also introduce distortion (without RTZ encoding).
Considering all above the DAC measures pretty well.
TCD
How does is sound is the question, say, compared to Holo Audio – May DAC | Kitsune HiFi - HoloAudio USA ?