To test for phase margin you need hardcore lab stuff like vector network analyzer, wide bandwidth injection transformer. Or a DSO with internal wavegen and special software option, again the injection transformer. You know its stable or not when it will be a flat line without riding waveform when simply scoping the rails with any scope though. How close to instability you don't know with simple equipment. Spice sim isn't too bad for prediction though.
Stability Analysis of Power Supplies with the Bode 100
Power Supply Control Loop Response Keysight InfiniVision X
No shorts.
Vbe transistors Q2, Q3 and Q4 test Ok. 0,6v. but Q1 Vbe=0,1v.
I replaced three times, now last one on board, I hope still healty, as I lowered CC R1=5R1 To match the healty UltraBib I have to power the amplifier (a
Tripath chip amp at 13v./63mA.). This way leds still light up. I would not attept to load it, as it cause to burn Q1.
I just set the same 13v. output on both boards, and still this way
not able to fix the damaged one.I mean I set the trim VR1 same value on both boards, but the damaged can't reach over 6v. (using same transformer, R1, etc..)
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R4 drop: I expect to find same 560mV. as in healty one, but instead, it is a higher value, starting in the beguining at 800mV. very unestable, and decreasing minute by minute, to 700mV. and 600mV. Further don't know, afraid to fry something.
Maybe is worth to mention, I see on R1 close to 0V. drop on healty one, but then in defective one, I set same 5R1 but 23,9v. input to 25,8v. leg output.
Ah! mosfet M1 checked! insulated.
Maybe is worth to mention, I see on R1 close to 0V. drop on healty one, but then in defective one, I set same 5R1 but 23,9v. input to 25,8v. leg output.
Ah! mosfet M1 checked! insulated.
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some days ago I resoldered J1 after confirm their health, right now I placed a brand new one but same.
It looks like the power supply has no load to transformer, because I get 24v. DC after diode bridge. Compared to the healty board (same bridge/ transformer, and same R1 / VR1 settings) I get a lower 22,4v. DC.
It looks like the power supply has no load to transformer, because I get 24v. DC after diode bridge. Compared to the healty board (same bridge/ transformer, and same R1 / VR1 settings) I get a lower 22,4v. DC.
No, a JFET isn't like a transistor so to have Vbe voltage. Without powering the board, use the Ohm meter and check every PF5102 with no need to desolder it, for 60-90 Ohm between its pins 1-2 and 270 Ohm between pins 2-3. Those are their healthy rough RDS readings and the good source resistors readings. Use four normal modern diodes -on board- maybe something goes wrong creating oscillations when connecting an external NOS selenium bridge.
I am running some final tests before powering up the DCG3. I notice that the overshoot for one of the negative shunts is up to -17.48V before it settles down to ~17V after 15-20 minutes. The other one doesn't do the same. Any logic to why? The component types used are exactly the same sans the tolerance factor.
Quick question...
I am planning on powering two a24 gain stage boards with +/-14 VDC. These boards in my use have two ICs (OPA 1612 & OPA 1632) with 100 uF electrolytic caps for each rail of each OPA. Total of 400 uF per rail will be seen by UBiB
I am considering just putting 1 uF instead of 100 uF on the boards for use with UBiB, for a total of 4 uF. Would this be sensible?
I am planning on powering two a24 gain stage boards with +/-14 VDC. These boards in my use have two ICs (OPA 1612 & OPA 1632) with 100 uF electrolytic caps for each rail of each OPA. Total of 400 uF per rail will be seen by UBiB
I am considering just putting 1 uF instead of 100 uF on the boards for use with UBiB, for a total of 4 uF. Would this be sensible?
I read all Ohms on PF5102 pins as they should. Then added diodes that come on kit, but the board is still defective. Every solder point is prefluxed, and after cleaned residue with alcohol. Also changed VR1, all resistors are reliable: BWL EE high precision resistor 0.1% non-inductive and low temperature drift.
Sorry...
I was not entirely clear: I am referring to the local electrolytic caps on the load side, there are 4 per rail of 100 uF each, and I propose to reduce them to 1 uF each.
The caps on the UBiB will be as specified.
I was not entirely clear: I am referring to the local electrolytic caps on the load side, there are 4 per rail of 100 uF each, and I propose to reduce them to 1 uF each.
The caps on the UBiB will be as specified.
But the other one you got works, right? Mysterious. The Mosfets are the right type confirmed in the sick one? The PMOS and NMOS positioned at their right places I mean. And they do show 4-5V Vgs on M1 and 3-4V Vgs on M2? Between first and last leg the Vgs of each can be measured when the system is powered.