^ Thanks for the info about the Japanese experiment, and if you stumble across any info about it, I'd appreciate a link (but don't go looking for it on my accord!). Otherwise, just wanted to mention we're in agreement, and I think you're vacuum-state DAC is pretty dang cool.
Really? You expect me to go through hundreds of datasheets to find your evidence that you're right? Are you a first year undergrad by any chance? ;-)
Are you aware that SRC is not OS? This dac uses an fpga to split left and right for separate DAC chips and updamples to 384/24 using a somewhat smooth interpolation. Its clocked using Crystek CCHD957.
^ http://www.analog.com/media/en/training-seminars/tutorials/MT-017.pdf
Might help with SRC and OS (they're all very interrelated)
Might help with SRC and OS (they're all very interrelated)
Yeah I'm not aware of any filterless implementation of sample rate conversion. I think the digital filter was the bogeyman, right?
Do you know that ALL reviews from the internet and magazines are paid?
In this case the results are not very important.
Yes, the whole idea of NOS they don't get the 44.1 data comes out at 44.1 and the rest is analog otherwise there is a digital filter.
I've also not seen such reports in any S-D DAC chips I've looked at. Multi-bit DACs though do show this effect but its jolly hard to find in the DSs because they don't in general characterize them at multiple sample rates, normally just the highest one.
Why don't you give us a concise technical description of each and how they are different.
You can see it in the PCM1792A datasheet and the AK449x datasheets. I haven't checked any Cirrus or ex-Wolfson parts. It looks to be the over the same measurement bandwidth. I agree that all these datasheets are lacking compared to the AD1955 which doesn't really show this effect.
internal vs external? Hmmm... a bit long, not wholly true. Pad vs fill? Shorter at 9 characters. I challenge you to do better. 🙂
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https://www.akm.com/akm/en/file/datasheet/AK4490EQ.pdf
Page 10; looks like they keep expanding the bandwidth as they up the sampling rate? Which case it's no surprise the THD+N goes up (N part at least!). It's a bit goofy representation of the data. I know JensH has characterized the 4490 very carefully so hopefully he can chip in on how it behaves at its respective sample rates.
Page 10; looks like they keep expanding the bandwidth as they up the sampling rate? Which case it's no surprise the THD+N goes up (N part at least!). It's a bit goofy representation of the data. I know JensH has characterized the 4490 very carefully so hopefully he can chip in on how it behaves at its respective sample rates.
Fill with what, pad with what? You have a hard time filling 44.1 to 384 the pieces don't fit and you need some maths can you fill these in?
I'm honestly unsure, to be fair. I remember reading it with your interpretation. Now I'm wondering what bandwidth they're using for the 0dBFS measurements. It does cleanly fall off at 3db per doubling of bandwidth...
It is indeed quite evident in the 1792A DS. So I visited some other DACs in the same PCM179X family and found something inconsistent. That is on the X=5 and X=6 parts the headline THD numbers for 96k and 192k don't at all correspond to the plots. The plots (fig11, fig15) show THD almost unchanged between sample rates (slightly worse at 192k but practically identical at 96k) and well below the 'headline' numbers in the earlier table for the higher rates.
Take the PCM1796 as example - fig15 (page 12) shows 96k THD+N at 0.0005% whereas the table (page 3) shows 0.001%, a 6dB discrepancy.
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