As standard built, 5V or bit under is the Ubib's output floor at VR1 minimum (depending on various parts tolerances). Read the build manual I uploaded in post#1.
If you would substitute M2 with a low threshold NMOS like the REF-D's MTP3055VL and jumper short the second LED you could go low towards 3.3V but the also lowered inner voltages will be squeezing J2 & J3's VDS space too much. Maybe with least IDSS samples that have smaller Vgs (off) it could work better. Also put R9 1k. Anyway pushing the 1.3 for too low Vout isn't the target range it was initially designed for to be at its best.
I know the pinouts are different. Other than that, is there any chance to use the Toshiba 2SK117GR in place of the PF5102? I have a couple hundred of the Toshiba's and would like to use them if I can.
Thanks!!
Sims show it should work with the 117s also and without phase margin problems. See to choose them for for 1.5-2mA Id with those 270R or use other value source resistors. The Zo curve may end up more irregular and taking off early but with lower μΩ at its valley region and its initial escalation region. With their smaller Vgs (off) they should be more at ease in the bottom part of Vout's low range too.
Thanks, Salas. That is good news.
Let see I read it right. To determine the Toshiba jfet and the source resistor combo, use
1. 9V battery
2. a source resistor, let say a 100R in series with a 500R pot.
3. measure the voltage across the 100R while adjusting the pot, aim at 0.15V - 0.2V.
4. Measure the resistance across the pot and add 100R, that will be source resistor for this jfet.
Does it sound right?
Thanks again!!
Let see I read it right. To determine the Toshiba jfet and the source resistor combo, use
1. 9V battery
2. a source resistor, let say a 100R in series with a 500R pot.
3. measure the voltage across the 100R while adjusting the pot, aim at 0.15V - 0.2V.
4. Measure the resistance across the pot and add 100R, that will be source resistor for this jfet.
Does it sound right?
Thanks again!!
The approach is valid but the resistance values maybe too high for most K117GR samples taking them to Id 1.5-2mA. At roughly an order of magnitude lower the resistors could be more practical for searching out such Id. Simpler would be just using a precise enough DMM in series mA mode between Vcc and drain as well as a 100R trimmer as source resistor.
It depends on the build. E.g: For reflector-D it is critical to do jfet mod and Led filtering cap must be of high quality. I even use 2xReflectord-D running @ -/+15V for i/v conversion board. I liked it better than BiB 1.1. Can wait to compare it new ultra ones
It depends on the build. E.g: For reflector-D it is critical to do jfet mod and Led filtering cap must be of high quality. I even use 2xReflectord-D running @ -/+15V for i/v conversion board. I liked it better than BiB 1.1. Can wait to compare it new ultra ones
which type of high quality caps do you recommend - for led filtering and after bridge
Mundorf MLytic AG+ 4 pin. Look for it on Salas Reflector D builds thread on this forum. Everything is there.
You should be able to set +/-15V DCout on the Ubib and still have a nice and safe 5V DC drop across the reg (Vc1-Vo) with those secondaries.