There were some op-amps designed for audio.
Well, said to be designed for audio.
Related details never known.
Come on now the first one is an RF amp.
Now for "designed for audio", let me dispel the myth that prototype chips go into the listening room for several rounds of tweeking by trained designer/listeners. Most would be surprised at how limited the component selection is there is no resistor formula tweeking, no mask revs to try for different sounds, this view of chip design is fantasy. It would cost 10's of thousands of dollars for even the slightest change.
Designed for audio is a functional description at best. In which case you could make an argument that the 5534 was designed for audio since the lack of bias current compensation cripples it for precision instrument applications but gives it a better SNR over a larger input impedance range.
Digital engines are different I know from the design team directly the ESS DAC was prototyped via FPGA through several revs. This is very different even the most sophisticated FPGA's are a couple of thousand dollars a rev.
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Ok, so perhaps that example is extreme, although I can see some geeks using that chip as a single ended to differential converter, perhaps not at the full 17,000V/us.
Now care to explain why the THS4022 is not good for audio? Min gain of 10 is not necessary an issue, although it may limit a little the application area. It would certainly satisfy the need for speed claimed by some for a MC amp (not that I believe those 450V/uS would make a iota of difference).
P.S. Not to mention that fig.5 shows an open loop gain bandwidth of over 50kHz 😉
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rayma,
We'll that just confirmed my thinking that this was terrible packaging. A couple of tall capacitors and one round battery. I've had to do some packaging for a cell phone device and you can get flat pack batteries in just about any shape you can think up. The package could have been half the size if done correctly.
We'll that just confirmed my thinking that this was terrible packaging. A couple of tall capacitors and one round battery. I've had to do some packaging for a cell phone device and you can get flat pack batteries in just about any shape you can think up. The package could have been half the size if done correctly.
If you test with a 5v square wave you overload the input. This should be obvious. The feedback has a delay.
Intigrated electronics (Millman and Halikis) define slew rate as "the time rate of change of the closed loop amp output voltage under large signal conditions.
They go on to say it's measured with a high freq. square wave.
If you have analysis and design of analog integrated circuits by Gray and Meyer read from page 541. It starts with " a common test of the high freq. large signal performance of an amp is to apply a step input voltage from 0 to 5 volts to the input of a unity gain amp." And goes on to explain what I've been saying.
Boring. I also see a 50 KHz 1/f corner. (if that's a corner. The plot stops at 100 KHz where it
is rising again.)
What if it had another 20 dB more gain at 5 KHz. Would that be better or worse?
40 dB more at 500 Hz?
There are other TI chips that impress me more.
regards, Gerhard
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I guess you did not note the tongue in cheek 😀.
A salesman questioned in #998 if there are low noise, high SR (100's V/uS) op amp chips. I just gave a random example of such a VFB op amp.
P.S. I think you missed my post #600. I'm truly interested in the topic.
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Gerhard your chance to be a hero, the guys at LIGO are looking for a .1nV op-amp. The catch is perfect DC operation like everything thermally tied on one chip, their composite amps have too much 1/f & DC wander besides they're stuck at the .3nV or so region. Seriously if you have any interesting out of the box ideas I'm meeting with Dr. Weiss on Oct. 11 and there is a team Germany prototyping the instrument package.
The true prop delay of feedback is nanoseconds or less the phase of input vs output vs frequency is another matter. We aren't going to go to the feedback goes round and round again?
The TI paper On slew rate is just an extension of what I've been saying. ( there first reference is the first book I quoted ). They just show a different way to measure it. If you look at the current thru the diff input transistors with a square wave input, initially one will have zero current ( it will be off, or into the flat parts of the tanh transfer function.) and this is input overload. Or the 2 text books I refer to ( and I'ld bet the guys who wrote the TI paper studied them) are wrong. And as you get into slew rate limiting I'ld bet the input transistors are getting close to turning off. Don't make me get the simulator out. Scott, do you have the Gray and Meyers text? Is it wrong? Or am I (and my prof) reading it wrong.
OK, back to post 600.
< https://www.flickr.com/photos/137684711@N07/29193737144/in/datetaken/ >
To take my design as an example: 2 pairs of IF3602 could have an Idss of > 4A together and the alternate use of 16 BF862 might also approach 400 mA worst case. (ok, my BF862 average at 13 mA each). That is clearly too much to handle. gm rises with the root
of Id, but in a linear way with the number of transistors.
You can't even measure IDss of the Interfet thingies without a pulsing curve tracer or without frying them ( at reasonable Vds).
According to the Spice models, the IF3602 could bring me to < 150 pV/rtHz, but even the
0.25 Ohm source resistor that I need to inject the feedback costs me 65 pV. Ok, it adds
up geometrically.
There is no way to use source resistors large enough to control Is without spoiling
the noise behaviour, because their thermal noise would add directly to the input. So
there is only the gate left to reduce Is to something acceptable.
But if you introduce some gate bias, you cannot reference the gate to GND any longer.
--> an input coupling capacitor is necessary. But then, with a 100 Meg bias resistor,
a 10uF foil cap brings you into mHz territory. Important in my case (metrology).
BTW. ON semi has recently rolled out some new JFET chips, some of them seem to be
even slightly better WRT gm and Cin than BF862. But they do not publish nV/rtHz
Sorry, type numbers are to long to remember. Some other new On types are old Sanyo stuff (I read on usenet).
regards, Gerhard
(thinking about bootstrapping the hell around an array of IF3602 to get rid of the
huge capacitance, but that's like herding a flock of squirrels. Would also cost sqrt(2) noise performance.)
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So what happens to a square wave. Prop delay or phase delay? Does it matter. The signal at the -ve input stays at bias(0v) while the the positive input is at 5 volts. This completely turns one of the input transistors off.
Don't worry you are OK, it's just that the distinction of being in overload has more than one interpretation. Usually input overload is taking the inputs outside of their specified operating range. You're overthinking this, most of what you say is correct it's just semantics at some level. Many amplifiers are very benign and if you give them a square wave input they slew at their slew rate to the output level. Yes that's where one side takes all the current.
Scott, my ego thanks you. Yes I refer to input overload during slew rate limiting and believe , ulike many here, that slew rate has very little to do wit sound quality because the amp is no longer in the small signal/ linear region it was designed to operate in. So as long as it's high enough, increasing it further will do nothing. There, finally got to my point.
OK, back to post 600.
< https://www.flickr.com/photos/137684711@N07/29193737144/in/datetaken/ >
To take my design as an example: 2 pairs of IF3602 could have an Idss of > 4A together and the alternate use of 16 BF862 might also approach 400 mA worst case. (ok, my BF862 average at 13 mA each). That is clearly too much to handle. gm rises with the root
of Id, but in a linear way with the number of transistors.
You can't even measure IDss of the Interfet thingies without a pulsing curve tracer or without frying them ( at reasonable Vds).
According to the Spice models, the IF3602 could bring me to < 150 pV/rtHz, but even the
0.25 Ohm source resistor that I need to inject the feedback costs me 65 pV. Ok, it adds
up geometrically.
There is no way to use source resistors large enough to control Is without spoiling
the noise behaviour, because their thermal noise would add directly to the input. So
there is only the gate left to reduce Is to something acceptable.
But if you introduce some gate bias, you cannot reference the gate to GND any longer.
--> an input coupling capacitor is necessary. But then, with a 100 Meg bias resistor,
a 10uF foil cap brings you into mHz territory. Important in my case (metrology).
BTW. ON semi has recently rolled out some new JFET chips, some of them seem to be
even slightly better WRT gm and Cin than BF862. But they do not publish nV/rtHz
Sorry, type numbers are to long to remember. Some other new On types are old Sanyo stuff (I read on usenet).
regards, Gerhard
(thinking about bootstrapping the hell around an array of IF3602 to get rid of the
huge capacitance, but that's like herding a flock of squirrels.)
I have zero experience with the Interfet parts, but 8xbf862 running close to idss are about 0.3nV/rtHz and wouldn't take more that 100mA for average Idss values (mine are also around 12mA). Make them run at 1mA by biasing the gate using a 500Meg resistor (not a source resistor) and you are at 0.45-0.5nV/rtHz. Corner frequency decreases though.
The only advantages of running jfets at low current that I was able to find are less thermal low frequency gain fluctuation, a lower noise corner frequency (which could also be thermal related?) and the possibility to power the circuit from batteries. Noise wise, given a noise spec, running at low current is IMO a waste of otherwise perfectly fine low noise jfets. Not to mention the lower gm of the low noise stage, which btw is ~SQRT(Idss*Id) for single ended, so Idss matters, anyway.
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Yes this is an under-explored concept sort of the noise (or statistical variation) of temperature due to heat flow. I plan to to put his to the best minds in the world.
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