The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator

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1. Just before the 74HC04 in the "rutgerS'Clock" schematic on p. 6 there's a voltage divider consisting of two 22k resistors and a 1 uF capacitor. Assuming that one is within the passband of the 10uF//100nF decoupling capacitors of the 6.5 VDC supply then the cut-off frequency of the two 22k & 1 uF capacitor will be ~14 Hz (22k//22k). Won't this cause some LF instability of the oscillator, i.e. exactly in the frequency range where the oscillator should be stable? To this end: Would it be an idea to increase the 1 uF to e.g. 100 uF and thus lower the cut-off point?
Jesper, in the schematic I see the voltage divider and the supply of the 74HC04 on the same line and (in my opinion) influencing each other. Would there be some improvement to be expected if the divider was powered by it's own LC?

Greetz,
Edwin
 
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Hi Edwin,

Jesper, in the schematic I see the voltage divider and the supply of the 74HC04 on the same line and (in my opinion) influencing each other. Would there be some improvement to be expected if the divider was powered by it's own LC?

Greetz,
Edwin

... I think there could be an improvement but I'm not sure how much difference it would make in practice ... The HC04 triggers on the slope of the clock signal and maybe it won't matter in practice (i.e. I don't know ;-) ) ... Personally, I would increase the 1 uF capacitor to a value where the cut-off frequency was so low (= the 22k resistor division point so stable) that it is was unlikely to matter ...

Cheers,

Jesper
 
Hi Edwin,



... I think there could be an improvement but I'm not sure how much difference it would make in practice ... The HC04 triggers on the slope of the clock signal and maybe it won't matter in practice (i.e. I don't know ;-) ) ... Personally, I would increase the 1 uF capacitor to a value where the cut-off frequency was so low (= the 22k resistor division point so stable) that it is was unlikely to matter ...

Cheers,

Jesper
Jesper, I understand your point. but, since HF characteristics of electrolytes are not that ideal, it would probably be a good alternative to parallel it with a good foil or ceramic type, thus limiting the amount of HF-noise on the divided voltage. Ok, I understand... adding to the number of components and cost ;)

Cheers,
Edwin
 
a lot of questions...

Puuuh, there are a lot of questions...
First of all, I worked already 20 years on oscillators for radio applications and more than 3 years on this 11 MHz Xtal oscillator, so it is impractable to discuss all side-paths I followed.
One thing should be clear: the power supply of the 74HC04 MUST be as clean as possible because of the voltage dependent delay of it. Use a TentLabs parallel stabiliser (Shunt Regulator)
I use a 74HC04 because it is a splendid isolater to the outside world so that this 'load' cannot influence the oscillator.

I ended with NP0 chip capacitors after mica, polypropylene, teflon, glass, name it, and found out that the NP0 chips satisfied because the Xtal is the determining piece!!!
The decoupling cap of 1uF on the voltage devider at the entrance of the 74HC04 (which I forgot the implement on the PCB-layout) is high enough because the supply of the 74HC04 is made with the TentLabs parallel regulator, end so on end so forth....

About the effect of the oscillator jitter on the audio....
Read: https://www.by-rutgers.nl/PDFiles/Audio Jitter.pdf

As far as I know, there is no measuring method on the audio behind a DAC which gives insight into the relation between the audio quality and the noise spectrum of the clock oscillator. The only way is: listen to the generated stereo signal with a very good Audio equipment. After many years listening with many people we discovered that the close in noise of the clock oscillator is responsable for the clarity of the sound and the detailed sound stage (also in depth). It is even not quite clear which noise spectrum is desired. The only estimation is that there should be no correlation between the eventually audio and the noise, so be carefull with SPDIF signals (= input of a DAC) because they correlate with the audio. Listen to it with a headphone and you will understand what I mean.
Cheers,
Herbert.

BTW.: is there anybody who can tell how to implement an English spell checker on this foruM?
 
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@ Herbert Rutgers:

BTW.: is there anybody who can tell how to implement an English spell checker on this foruM?

Hi Herbert - & many thanks for your reply! I can see that it answers most of my questions maybe except one (I briefly ask this below) ...

However, first - in reply to your question about a spell checker for this forum - I took the liberty of doing a Google search - which to my eyes didn't really return a very useful reply. Yet maybe this page may be of help if it is feasible for you to paste the relevant text into a .txt document. I couldn't make the website part work but the .txt part appears to work in terms of identifying the spelling errors in a trial document.

Free Online Spell Check Tool

And then my question which I would appreciate if you can just answer in short:

- Are there any particular considerations to observe when laying out the board? I'm particularly thinking about the placement of the components in the left part of the schematic i.e. up to the 10 pF ("Ck") leading towards the 74HC04 ... It looks as if there could be some deliberate spacing between some components ...

To my knowledge no further questions ;)

Cheers,

Jesper
 
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To Herbert ... Since reading this:

Puuuh, there are a lot of questions...

... I've been thinking that if you find that e.g. I have already asked too many questions then please feel welcome to not reply to my last question.

As it is I'm already grateful for the information and insights that you (and others) have provided here and in general do not wish to ask people to do things that is not feasible to them ... should it be so in this case.

Cheers & thanks again ;)

Jesper
 
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Low frequency phase noise should evidence itself as modulation of low frequency signals. A way to check that would be to measure the cycle to cycle timing of a low frequency tone. It will be a week or so to get the stuff together and running but I can do that to pretty high precision.
 
@ Herbert Rutgers:

- Are there any particular considerations to observe when laying out the board? I'm particularly thinking about the placement of the components in the left part of the schematic i.e. up to the 10 pF ("Ck") leading towards the 74HC04 ... It looks as if there could be some deliberate spacing between some components ...

Jasper, I do not really understand your question. The print is about as large as a stamp..!! The only thing I tried to draw there is that the groundplane on the double sided PCB is not in the area of C', C'', Ck, Xtal etc. to lower the capacitance between the very high ohmic circuit parts and ground via the rather bad material of the PCB for HF.
Cheers,
Herbert.
 
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The steadiness of the signals would suggest that there is no low frequency modulation but if you hear a difference from close in phase noise that would be how it must manifest itself. What I can do is measure the cycle to cycle timing variation to PPB and see how much there is. Its difficult and there are a number of things that can affect it. I have used this technique as well as the classic FFT of a sine locked to the sample rate to see the close in phase noise. It takes a long measurement, large FFT to see something.

Usually doing this highlights a lot of other small but significant issues to sort out. I have found power line modulation from ground returns, divider triggered modulations etc. Those should be cleaned up regardless and maybe they are the real cause of audio degradation. Regardless, if its not in the analog output how can it affect things?
 
and maybe they are the real cause of audio degradation. Regardless, if its not in the analog output how can it affect things?

maybe, yes: maybe, but this is not the problem! The kind of distortion that phase noise makes in the audio is explained in:
https://www.by-rutgers.nl/PDFiles/Audio Jitter.pdf and
https://www.by-rutgers.nl/PDFiles/clock_jitter_spec-1.pdf
but why the human ear is so sensitive for this kind of distortion is still not explained (in the literature).
Herbert.
 
maybe, yes: maybe, but this is not the problem! The kind of distortion that phase noise makes in the audio is explained in:
https://www.by-rutgers.nl/PDFiles/Audio Jitter.pdf and
https://www.by-rutgers.nl/PDFiles/clock_jitter_spec-1.pdf
but why the human ear is so sensitive for this kind of distortion is still not explained (in the literature).
Herbert.
Herbert,

thanks for the document references. I've read them. The technical explanation of Jitter is clear, but I have some difficulty to translate the technical to the audible.... Could you please try to explain in some key-words how to perceive jitter? Perhaps other people could be helped by this explanation too...

Cheers,
Edwin
 
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@ Herbert ...

The only thing I tried to draw there is that the groundplane on the double sided PCB is not in the area of C', C'', Ck, Xtal etc. to lower the capacitance between the very high ohmic circuit parts and ground via the rather bad material of the PCB for HF.

Thanks again for the feedback - and the information you provide - Herbert. So I reckon there are no particular "aspects" to consider when laying out a PCB for an oscillator - other than the general guidelines for good HF design (and leaving out the ground plane in certain areas - right ... ?) ...

Cheers,

Jesper
 
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