Ah, thank you! I viewed it incorrectly. Your schematic is connected like the BJT complementary feedback pair! The first device (NJFET) acts as a follower, and the second device (PMOS) acts as a current booster. The first ~ 3mA of current passes through the NJFET and the 1K resistor. When more than 3mA flows, the IR drop across the 1K is 3 volts, which is sufficient to turn on the PMOS. And then the PMOS conducts all the rest of the current. (2V < Vthreshold < 4 volts; midpoint is 3 volts).
Are you concerned that the PMOS Gate-to-Source capacitance (about 800pF according to Vishay's datasheet) is driven by a stage biased at only 3mA?
BTW Helmut responded that the remaining small difference between the two loop gain analyses (with his modifications)
I haven't looked closely at Ketje's suggestions but will do. I did drop the dc level shift into the AD797 circuit. Of course, it did upset loop gain stability. This required the removal of the 120uF cap and inserting a 4.7pF cap from the inverting input of the op-amp to its output. Results below. They seem very impressive.
Frankly it would seem easier, and more appropriate, to run with the Linear Technology/Sennewald approach.
I haven't looked closely at Ketje's suggestions but will do. I did drop the dc level shift into the AD797 circuit. Of course, it did upset loop gain stability. This required the removal of the 120uF cap and inserting a 4.7pF cap from the inverting input of the op-amp to its output. Results below. They seem very impressive.
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BTW the attached is why I've been so focused on Vdrop. Given my peak load spec of 5A, the SOA of the pass transistor I have in mind limits Vds for continuous operation at somewhere between 6v and 7V.
However, I think the much broader issue is controlling Vin for a best-performance 3.5v<Vdrop<6v is fine if the incoming voltage has been regulated to some extent. It's likely not ideal, however, for regulating Vin which has only been smoothed with a set of filter caps and which will fluctuate with mains voltage; the available variance in Vin is far too tight.
A very simple solution to this issue would be to bang the incoming Vin through an LT1084 and, if the end target is 12V, output 16v ahead of this regulator. It also seems to me to have the advantage of internal current limiting at circa 6A (to be checked) which offers some protection for the pass device in this circuit. In this context, finessing Vdrop by a volt or so more seems to have low expected returns.
Of course this would also allow this regulator to be designed as a separate board which would likely be of use to many more people than my little project.
Thoughts?
However, I think the much broader issue is controlling Vin for a best-performance 3.5v<Vdrop<6v is fine if the incoming voltage has been regulated to some extent. It's likely not ideal, however, for regulating Vin which has only been smoothed with a set of filter caps and which will fluctuate with mains voltage; the available variance in Vin is far too tight.
A very simple solution to this issue would be to bang the incoming Vin through an LT1084 and, if the end target is 12V, output 16v ahead of this regulator. It also seems to me to have the advantage of internal current limiting at circa 6A (to be checked) which offers some protection for the pass device in this circuit. In this context, finessing Vdrop by a volt or so more seems to have low expected returns.
Of course this would also allow this regulator to be designed as a separate board which would likely be of use to many more people than my little project.
Thoughts?
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727R is not a standard E96 resistance value (nor E192 either). The nearest E96 values are 715 and 732.
35R is not a standard E96 resistance value (nor E192 either). The nearest E96 values are 34R8 and 35R7.
You might want to experiment with a capacitor between Vin and J2 gate+source. Try values between 100pF and 100uF (".STEP PARAM"), I think you may find you prefer 10uF rather than 0pF.
?? Connect J1 to C6 and get yet more filtering ?
Has Walt Jung told you why he included the 10 ohm resistor R3 in his Super Regulator? Why have you omitted it here?
Have you given any thought to installing a series resistor (perhaps fitted with a "ZerOhm" jumper resistor in the final design) between the MOSFET gate and the circuits which drive it? Why or why not?
Since the dynamic output resistance of Q2 is much higher than the dynamic output resistance of J1, you could rip out J1, replace it with a copy of Q2+R8, and get better attenuation / ripple rejection, from Vin to Vref.
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35R is not a standard E96 resistance value (nor E192 either). The nearest E96 values are 34R8 and 35R7.
You might want to experiment with a capacitor between Vin and J2 gate+source. Try values between 100pF and 100uF (".STEP PARAM"), I think you may find you prefer 10uF rather than 0pF.
?? Connect J1 to C6 and get yet more filtering ?
Has Walt Jung told you why he included the 10 ohm resistor R3 in his Super Regulator? Why have you omitted it here?
Have you given any thought to installing a series resistor (perhaps fitted with a "ZerOhm" jumper resistor in the final design) between the MOSFET gate and the circuits which drive it? Why or why not?
Since the dynamic output resistance of Q2 is much higher than the dynamic output resistance of J1, you could rip out J1, replace it with a copy of Q2+R8, and get better attenuation / ripple rejection, from Vin to Vref.
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Yes, that's about it.And 800pF driven from 1k gives -3dB point around 200kHz.If you like that higher, put in a BF245C with lower series resistor.Mark Johnson said:
Origionally my idea was to use a LM431 ,the opa solution was a copy what was presented here,to not change everything.It's possible that there now is a start-up problem and a need for a pull-up resistance at the output of the opa.
The LM431 brings back the level-shift.That's for keeping the min.1mA Iz when Vgs comes near zero.
Mona
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Attached are SOA curves for a few Nchannel MOSFETs. I've placed a red dot on each one, at a conservative evaluation point (5 amps @ 10 volts) that is beyond your requirements.
In my opinion, each of these MOSFETs falls in the top 10% of high-gain, high-fT power MOS devices. But hey that's just my opinion.
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Yes, yes. Not at that level of refinement yet. 727R was merely there to solve for 12V. Of course final resistors need to be available values. I will change the 35Rs now.
Will have a look. Thanks.
Looked at this. While I did not ask Walt, I understand it is a typical "trick" for helping phase margin with an op amp. In this case, a resistor was not beneficial for stability and worsened PSRR. The next standard 'trick' is a cap from -Vin to Out of op amp. 4.7pF placed there helped phase margin a lot (alongside of deletion of the 120uF cap).
Err, no. What would be the goal? Any resistance in series with the op amp output reduces PSRR at 2kHz and above. I will check if there's a phase margin gain to be had which allows the return of the 120u cap but given the above I don't think so.
ok thanks - will have a look
Yes, yes. Not at that level of refinement yet. 727R was merely there to solve for 12V. Of course final resistors need to be available values. I will change the 35Rs now.
Will have a look. Thanks.
Looked at this. While I did not ask Walt, I understand it is a typical "trick" for helping phase margin with an op amp. In this case, a resistor was not beneficial for stability and worsened PSRR. The next standard 'trick' is a cap from -Vin to Out of op amp. 4.7pF placed there helped phase margin a lot (alongside of deletion of the 120uF cap).
Err, no. What would be the goal? Any resistance in series with the op amp output reduces PSRR at 2kHz and above. I will check if there's a phase margin gain to be had which allows the return of the 120u cap but given the above I don't think so.
ok thanks - will have a look
Thanks. I was just now going through the NXP website looking at those with better SOA characteristics, low gate capacitance and relatively low RdsOn which weren't preloaded in LTspice. You've helped speed up that process and I will check the ones you list first. My current model uses the BUK9K35-60E (previously I had used the BUK9K52-60E but the 35 has about as good performance with an extra volt of SOA). I had already noted that the package was a big influence on SOA (e.g. DPAK versus LFPAK56D).
(The model with the TL071 was using the PSMN6R0-30YL)
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Interesting choice between 10u and 100u. See attached. Latter seems better overall to me. EDIT: I need to think about why this makes such a difference.
J1 to C6 was a no go.
I guess there's a trade between replicating the full current mirror or biasing the new Q2 with an LED and resistor a la Jung/Didden. (Part count increasing at a lovely rate...)
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Don't forget that current mirrors are inherently one-input, multiple-output networks. It's just that audio designers often choose to operate their mirrors with one-output. Look inside the guts of your favorite opamps; you'll see multiple-output current mirrors all over the place.
In your discrete component voltage regulator, if you consider input current to be IDSS_J2, you can mirror that current out as many times as you like.
In your discrete component voltage regulator, if you consider input current to be IDSS_J2, you can mirror that current out as many times as you like.
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Certainly. Perhaps with a potentiometer to let you fine tune the voltage at the intermediate node, while observing the actual raw-DC input waveform peaks and troughs on a scope, while connected to the actual load. You could adjust the pot, either to evenly split the power dissipation between the two regulators, or to achieve a desired max case temperature on one or the other pass element.
You could consider adding Fred Dieckmann's one-transistor improvement to 3-terminal regulators to get a lot better ripple rejection in the first stage. It installs an emitter follower capacitance multiplier, achieving much MUCH lower impedance at the ADJ pin, both at DC (thanks to the emitter follower) and also at AC (thanks to the cap multiplier). Choose R1 to get ~ 60 mA flowing in the emitter follower and then calculate its output resistance @ DC. Cowabunga! The 2SB772 might be a pretty good choice for Q1: good power dissipation (TO-126) and high beta. You want high beta in a capacitance multiplier; the higher the beta, the higher the permissible resistors in the base circuit, the bigger the RC timeconstant at the base, the lower the AC impedance. As the day follows the night.
In fact you could think seriously about making BOTH regulation stages out of LT1084s. You'd get >140dB attenuation of input ripple, and a simple circuit with low parts count. To add your own unique design twists, you could sprinkle in some ferrite beads, with or without resonance-killing resistors. Maybe a couple of 0.05 ohm resistors + 10,000uF capacitors here and there. Boom, done.
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I didn't get the chance to do anything on this over the weekend but just now I took a look at these.
The first is "end of life" and not available from my favourite supplier Mouser UK. I could not find a Spice model for it either.
I'm still looking for a Spice model for the second also. It is available, however - £1.22 per piece.
The fourth doesn't perform so well. See first chart attached.
The third is likely interesting. See second chart attached which compares the performance of the two NXP devices I had been looking at and the IPP037N06L3 (£1.83 for one at Mouser UK). The latter isn't as good but given the Vds headroom, may well be a better choice.
(LTspice provides an easy way to use .step to compare .model statements but unfortunately it doesn't allow stepping through a mix of .model and .sbckt so I can't put both these charts on one without exporting the data.)
PS: all without yet making the current mirror amendments
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However the IPP037N06L3 in the circuit as is doesn't provide the required phase margin. The 4.7p capacitor likely needs to increase significantly. (If it were to increase to 20p phase margin is c55 degrees and gain margin is about 6.6dB and, of course, there is a decrease in PSRR performance.)
Maybe you simply want to put two of your post#83 MOSFETs in parallel; this will cut the per-device power dissipation in half, and it has a good chance of giving satisfying performance on the other measurements too. Worth a try. If it's good you can just buy an extra 3 MOSFETs (if you need 4, buy 7) and create matched pairs as best you can. Even if they don't perfectly match, and one transistor conducts 2/3rds of the total current while the other conducts 1/3rd, that's still a 1/3rd reduction in power. You could simulate this using a deltaVthreshold voltage source in series with one gate but not the other.
You can of course embark on your own search for suitable MOSFETs. First try the ones whose models you've already got; maybe one of them is acceptable. If not then happy hunting on the web.
You can of course embark on your own search for suitable MOSFETs. First try the ones whose models you've already got; maybe one of them is acceptable. If not then happy hunting on the web.
Perhaps the ripple rejection is better with the capacitance multiplyer,the voltage reference becomes 1.25V of the IC + Vbe of the transistor,less stable (temp.!)
Also another thing I forgot to say,the cicuit I proposed has a sort of build-in current limit.The max current in the Jfet at Vgs=0 is Idss.That gives a max Vgs for the Pmos across the Jfet drain resistance.By chosing the right value the current in the Pmos can be limited.
Mona
Also another thing I forgot to say,the cicuit I proposed has a sort of build-in current limit.The max current in the Jfet at Vgs=0 is Idss.That gives a max Vgs for the Pmos across the Jfet drain resistance.By chosing the right value the current in the Pmos can be limited.
Mona
Therefore: subtract out the Vbe!
A cascade of two emitter followers has even more current gain (higher effective beta) than a single transistor. And, if we make one of them NPN and the other PNP, the Vbe drops cancel out. See attached figure.
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That's a possible approach. With an 18V secondary, a couple of 30mR series resistors and 3x 0.47Ohm resistors between smoothing caps, I have a voltage range from about 16.8v (low end of mains range and full load) to 26v (high end of mains range and minimal load) to contend with. (That ignores variance in the resistors.) The challenging part of that spectrum is full 5A load and high end of mains voltage - circa 21v ahead of the regulator. 9v is on the DC line of Vds versus Id for 3A.
Or I break the task into two with a pre-regulator. I must admit I am somewhat inclined to keep any pre-regulator simple, if only to get something built sooner (or actually built!). The Mosfet based regulator has more than enough PSRR.
I've spent quite a bit of time going through the NXP Mosfets trying to find a better combination of SOA, Qg, RdsOn, Ptot but nothing I have yet tried comes close to the BUK9K35-60E. BTW this is already a dual N-MOSFET. (Hmm, maybe that's a variable worth focusing on when searching for alternatives.) I presume when I select it in LTspice and use it as a single FET it means the two are joined (i.e. all drain, gate and source pins joined, respectively) or is this just a model of one of the channels?
Before I go much further, I have a question regarding this device's package. It is a plastic single ended surface mounted LFPAK56D (8 leads). See first attachment. I am not familiar with this package. Google found me the second attachment. Any other thermal/mounting considerations, e.g. larger (but masked) copper drain area to keep temp down?
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is this [LTSPICE model] just a model of one of the channels?
Ask your assistant to simulate one of the IV curves in the datasheet using the LTSPICE model. Is the simulation closer to 0.5X, 1X, or 2X the published IV curve? If it's obvious then you have your answer. If it's not obvious then you have a cudgel to smack the NXP applications engineering department.
Sorry I have no advice to give on the thermal question.
Ask your assistant to simulate one of the IV curves in the datasheet using the LTSPICE model. Is the simulation closer to 0.5X, 1X, or 2X the published IV curve? If it's obvious then you have your answer. If it's not obvious then you have a cudgel to smack the NXP applications engineering department.
Sorry I have no advice to give on the thermal question.
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