BTW I laboriously went through every MOSFET in LTspice by International Rectifier. Of course it had to be the very last one, but this one shows some promise for applications with lower voltages (for a 12v reg, at start-up Vds is above 12V given the source is sitting at ground): IRLR3802PbF/IRLU3802PbF.
It has almost identical performance to the NXP BUK9K35-60E. It comes in either D-Pak I-Pak. Mouser UK only stocks the D-Pak.
Absolute max Vds is 12v and Vgs +/- 12v. I'm not sure how one would manage thermals with these packages.
It has almost identical performance to the NXP BUK9K35-60E. It comes in either D-Pak I-Pak. Mouser UK only stocks the D-Pak.
Absolute max Vds is 12v and Vgs +/- 12v. I'm not sure how one would manage thermals with these packages.
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Of course it's impossible to know with perfect certainty, what the NXP datasheet writer was attempting to convey. One MOSFET? Both MOSFETs operated in parallel? It's also impossible to know whether they made errors in preparation of the datasheet.
Similarly it's impossible to know what the .MODEL parameter extraction team was trying to do. Model one MOSFET? Model both MOSFETs operated in parallel? It's also impossible to know whether they made errors when extracting the model parameters.
However it is possible to ask and answer questions like "What applications might want two independent NMOS FETs in a single package?" "Why would they want two independent FETs instead of a single FET with half the RDSon?" "What data would these customers desire to see on a datasheet? Would they prefer to see measurements of one FET operated individually, or both FETs operated in parallel?"
It is also possible to imagine a few possible outcomes of simulation-vs-datasheet comparison experiments, and to suggest possible interpretations. Such as:
I spent 15 minutes horsing around on Mouser UK looking for NXP dual NMOS FET datasheets, in which it was dead obvious whether the measured data represented one individual FET, or both in parallel. Clearly I didn't investigate every single product NXP sells - that would take more than 15 minutes. But I did find the PMGD280UN which is a dual. Very fortunately, NXP + MouserUK also sells the PMF280UN which is the same FET as a single. You can compare the datasheet I-V curves of the Dual and the Single to see whether NXP plots both FETs in parallel, or one FET individually.
I also found the BSS138PS which is an NXP dual NMOS FET on Mouser UK. They also sell the BSS138PW which is the same FET as a single. I-V comparisons between the two datasheets are enlightening.
Similarly it's impossible to know what the .MODEL parameter extraction team was trying to do. Model one MOSFET? Model both MOSFETs operated in parallel? It's also impossible to know whether they made errors when extracting the model parameters.
However it is possible to ask and answer questions like "What applications might want two independent NMOS FETs in a single package?" "Why would they want two independent FETs instead of a single FET with half the RDSon?" "What data would these customers desire to see on a datasheet? Would they prefer to see measurements of one FET operated individually, or both FETs operated in parallel?"
It is also possible to imagine a few possible outcomes of simulation-vs-datasheet comparison experiments, and to suggest possible interpretations. Such as:
- Suppose you simulated a single instance of the MOSFET model. Suppose its I-V curve is just about exactly 2X the I-V curve in the datasheet. That probably means ... (something)
- Suppose you simulated a single instance of the MOSFET model and suppose its I-V curve is just about exactly 1X the I-V curve in the datasheet. That probably means ... (a different thing)
- Suppose you simulated a single instance of the MOSFET model and supose its I-V curve is just about exactly 0.5X the I-V curve in the datasheet. That probably means ... (a third thing)
I spent 15 minutes horsing around on Mouser UK looking for NXP dual NMOS FET datasheets, in which it was dead obvious whether the measured data represented one individual FET, or both in parallel. Clearly I didn't investigate every single product NXP sells - that would take more than 15 minutes. But I did find the PMGD280UN which is a dual. Very fortunately, NXP + MouserUK also sells the PMF280UN which is the same FET as a single. You can compare the datasheet I-V curves of the Dual and the Single to see whether NXP plots both FETs in parallel, or one FET individually.
I also found the BSS138PS which is an NXP dual NMOS FET on Mouser UK. They also sell the BSS138PW which is the same FET as a single. I-V comparisons between the two datasheets are enlightening.
My presumption is that for many items it would be characteristics of each FET. But this is nothing more than a guess. However, for others, e.g. power dissipation, I might rather expect to know what the total device dissipation is rather than presume it's double the per transistor values. At least with the BSS138PS datasheet things are clear. To my mind, the presentation there is simply common sense.
This is circular. If I DC sweep a single instance of the BUK9K35-60E I get a result that more closely resembles 1x the datasheet graphic rather than 0.5x or 2x. The only thing that leads me to believe that this is just one FET is that LTspice doesn't appear to have a symbol for a dual channel FET and the model for the BUK9K35-60E only has 1 set of pins - the only way to model dual channel behaviour, with independent behaviours on each channel, is with two instances of the device in LTspice.
The former is helpful for inference. The presentation of the BSS138PS makes a lot more sense. The BSS138PS datasheet undermines confidence that the BUK9K35-60E term sheet shows per FET values.
After all that, my presumption is that the figures are per FET and now return to focusing on thermal considerations.
Do I have this correct or can the very initial situation be ignored? As soon as the regulator starts Vds falls below 12v.
Let's assume you will source the AD797 from a trusted and known-good supply channel: either free samples direct from ADI, or purchased units from one of their authorized distributors, or chips that Scott Wurcer personally places in your hand. Let's assume your AD797s are pristine new parts, fresh from the factory, and they pass all production tests & meet all datasheet specifications.
Even so, I expect that your actual AD797 units will not match the SPICE model. I expect that there will be differences between the actual chip's performance, and the simulated performance using the SPICE model.
This should not be a surprise.
I can think of three or four reasons why the SPICE model won't match the real silicon.
How many reasons can you think of, why the SPICE model doesn't match the real silicon?
Given that the SPICE model is not a perfect reflection of actual performance, what can you do about it during circuit design? If "blindly believing the SPICE model" results in a voltage regulator whose probability of success is "P", what else (if anything) can you do to increase the probability of success above P?
Even so, I expect that your actual AD797 units will not match the SPICE model. I expect that there will be differences between the actual chip's performance, and the simulated performance using the SPICE model.
This should not be a surprise.
I can think of three or four reasons why the SPICE model won't match the real silicon.
How many reasons can you think of, why the SPICE model doesn't match the real silicon?
Given that the SPICE model is not a perfect reflection of actual performance, what can you do about it during circuit design? If "blindly believing the SPICE model" results in a voltage regulator whose probability of success is "P", what else (if anything) can you do to increase the probability of success above P?
Presumably a start is to "overbuild" the bits it drives, e.g. the level shift, and the bits that drive it, e.g. Vref and Vs, and factor in good margins for stability.
I took another look at the IPP037N06L3 G given its TO-220 package. The performance (attachment 1) is still very good with the updates to the rest of the circuit and even with the larger cap from the inverting pin to the output pin of the AD797; increasing the cap from 4.7pF to 47pF provides good phase margin and 11dB of gain margin (attachment 2). Of course, I should have checked availability more carefully; while Mouser UK shows a price, they have no stock (and Farnell UK no longer stocks it). Lovely.
EDIT: RS Online happens to have 22 in stock
I took another look at the IPP037N06L3 G given its TO-220 package. The performance (attachment 1) is still very good with the updates to the rest of the circuit and even with the larger cap from the inverting pin to the output pin of the AD797; increasing the cap from 4.7pF to 47pF provides good phase margin and 11dB of gain margin (attachment 2). Of course, I should have checked availability more carefully; while Mouser UK shows a price, they have no stock (and Farnell UK no longer stocks it). Lovely.
EDIT: RS Online happens to have 22 in stock
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Yes, I decided to grab a half dozen plus a few LM4040 in 5v, 2.5v and 2v to bump the order up so as to not incur £5 postage. Better to have some of the voltage references "for free". At least that's a key variable bedded down.I need to re-read the section on bypassing the AD797... and model out the 5v and 3.3v regs.
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Here are a couple of diyAudio postings that advocate gate stopper resistors for source follower MOSFETs:
Written by Nelson Pass:
http://www.diyaudio.com/forums/pass-labs/262120-f5-gate-stopper-value-question.html#post4062309
Written by John Curl:
http://www.diyaudio.com/forums/soli...ff-based-irresponsible-advice.html#post213673
The Search facility will find many dozens more, if you are inclined to read further.
Written by Nelson Pass:
http://www.diyaudio.com/forums/pass-labs/262120-f5-gate-stopper-value-question.html#post4062309
Written by John Curl:
http://www.diyaudio.com/forums/soli...ff-based-irresponsible-advice.html#post213673
The Search facility will find many dozens more, if you are inclined to read further.
Thanks. I also read slup169.pdf from here.
I understand that the purpose of gate drive resistors is to dampen ringing of the Mosfet as it is switched on and off. This ringing exists because the "source inductor and the Ciss capacitor form a resonant circuit". The paper provides a formula for Rgate, optimum which depends on the source inductance of the Mosfet, Ciss, Rgi and the driver output impedance. It notes "smaller resistors will result in overshoot in the gate drive voltage waveform, but also result in faster turn-on speed. Higher resistor values will underdamp the oscillation and extend the switching times without offering any benefit for the gate drive design."
In this context, I (rightly or wrongly) perceive a risk to impairing the responsiveness of the Mosfet and hence reg PSRR from too high a gate resistance. This was apparent when I looked at resistors in series with the op amp output when (a) examining R3 in the Jung/Didden regulator and (b) the regulator's phase and gain margin and the impact of introducing an R3 equivalent into this circuit.
When I look at modelled waveform of Vgate and Vout while stepping the load from 0.1A to 4.9A and back again I see no evidence of under-damped oscillation with the IPP037N06L3 Mosfet (in contrast to that which was observed earlier, see post 48). This suggests to me that any natural resonance is already damped by driver circuit. See attachments.
Am I missing something?
PS: any gate resistor impairs PSRR from about 2kHz and up
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Yes you have made at least two mistakes. One of them is to omit the resonating inductors from your simulations and then conclude when you don't see resonance, all is well. Another mistake is to assume that the red resistor "R3" below is a base stopper resistor, and to further assume that replacing NPN Q1 with an Nchannel MOSFET, turns R3 into a gate stopper resistor. A third mistake is to overconfidently conclude that when your simulations do not agree with both Nelson Pass and John Curl, the error must be Nelson Pass's and John Curl's.
Why don't you read Bob Cordell's book p.194 & 206 (base stopper resistors), and also p.215 (gate stopper resistors). Then look at post 81 in this very thread; the 330 ohm resistor is a gate stopper. Then look at Fig 11.17 on page 242 of Cordell's book; that's Bob Cordell's MOSFET power amp. Study resistor R40 (100 ohms) at top right; that's a gate stopper resistor.
Why don't you read Bob Cordell's book p.194 & 206 (base stopper resistors), and also p.215 (gate stopper resistors). Then look at post 81 in this very thread; the 330 ohm resistor is a gate stopper. Then look at Fig 11.17 on page 242 of Cordell's book; that's Bob Cordell's MOSFET power amp. Study resistor R40 (100 ohms) at top right; that's a gate stopper resistor.
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Agreed, assuming the models don't model these effects.
Here I merely meant that any resistance in series with the gate/op amp output was detrimental to PSRR. When I was trying to understand the purpose/impact of R3 I tried adding such a resistor to the Mosfet circuit. This was before the level shift was present and so R3 was directly connected to the MOSFET gate. The impact to PSRR was readily observable. The question of a resistor at the output of the op amp came up again when looking at stability. The Linear Technology video I linked to some time ago includes a couple of tips for dealing with op amp stability, one of which is placing a resistor at the output of the op amp to roll off gain. It also "fits" with the discussion in the paper I linked to that such resistance slows the charging and discharging of the gate capacitance and the speed of the Mosfet. I was therefore not at all surprised to see that adding, for example, a 20 Ohm resistor at the gate of the Mosfet damaged PSRR.
No, I had merely questioned what I was missing and, at best implicitly, whether their recommendations were for a different sort of application.
My copy of Cordell's book is the Kindle version and hence does not have page numbers in the same way as the printed version. Nonetheless I found the section on gate stopper resistors and fig 11.17. I note that in section 11.4 Parasitic Oscillations / Gate Stopper Resistors Cordell comments "unfortunately, the practice of using gate stopper resistors discards one of the big advantages of the power MOSFETs, namely their speed." A critical component for a regulator of this type, no? And again not surprising that dropping in such a resistor greatly affects higher frequency PSRR. He goes on to comment that "these resistors are often on the order of 100-500 Ohms" the lower end of which matches the recommendations made by Pass. He later goes on to recommend Gate Zobel Networks "rather than just killing the high-speed performance of the MOSFET."
Note that before looking at the model, I did try to apply Balogh's formula to my situation. Unfortunately, while Ciss and Rgi are provided in the data sheet, Ls isn't that I could see. I would also have to estimate the impedance of the circuit driving the gate.
There is no measurable effect upon simulated circuit performance when Rgatestopper is 1E-5 ohms. There is tremendously bad circuit performance when Rgatestopper is 1E+5 ohms. But where is the midpoint? What is the largest Rgatestopper which still has no measurable (in simulation, using somebody else's MOSFET models, whose inductances you don't know) effect upon circuit performance? Call it Rx. Why on earth wouldn't you include a gatestopper of value Rx in your simulation and more importantly on your PCB? This makes it possible to swap in any value of Rgatestopper you like (including zero ohms, or Rnelsonpass ohms, or Rjohncurl ohms) on your real board in real life, if you see too much resonance or too little resonance when you measure the real thing with a real load.
Make sure to connect Rgatestopper correctly in simulation; don't screw this up. Make sure there is absolutely no circuit path from the MOSFET gate to any other component, except through the series Rgatestopper.
You could ask your assistant to devise a set of simulation experiments, which will extract the values of gate inductance, drain inductance, and source inductance of a given MOSFET subcircuit or model. This has the advantage that you don't have to trust the documentation of the simulator or the documentation of the model. You simply run your own tests and trust your own results. If your MOSFET's simulated behavior is indistinguishable from Lgate = 8 nanohenrys, then Lgate IS 8 nanohenrys. If it walks like a duck and quacks like a duck, it's a duck. When completed you will know whether or not your particular MOSFET model includes inductances; and if it does, you will know their values. Comforting.
Make sure to connect Rgatestopper correctly in simulation; don't screw this up. Make sure there is absolutely no circuit path from the MOSFET gate to any other component, except through the series Rgatestopper.
You could ask your assistant to devise a set of simulation experiments, which will extract the values of gate inductance, drain inductance, and source inductance of a given MOSFET subcircuit or model. This has the advantage that you don't have to trust the documentation of the simulator or the documentation of the model. You simply run your own tests and trust your own results. If your MOSFET's simulated behavior is indistinguishable from Lgate = 8 nanohenrys, then Lgate IS 8 nanohenrys. If it walks like a duck and quacks like a duck, it's a duck. When completed you will know whether or not your particular MOSFET model includes inductances; and if it does, you will know their values. Comforting.
Ok granted re first point although I have a reluctance to have to jumper over pads which I suspect I have to get over.
Infineon use 2n for Ls in their IPP037N06L3 model (Ld=2.5n, Lg=4n). Ciss from the datasheet is 10,000pF. Rgi = 1.3 Ohm
Rgate,opt = 2 x SQRT(Ls/Ciss)-(Rdrv+Rgi) = 2 x SQRT(0.2) - Unknown - 1.3 = less than zero
Infineon use 2n for Ls in their IPP037N06L3 model (Ld=2.5n, Lg=4n). Ciss from the datasheet is 10,000pF. Rgi = 1.3 Ohm
Rgate,opt = 2 x SQRT(Ls/Ciss)-(Rdrv+Rgi) = 2 x SQRT(0.2) - Unknown - 1.3 = less than zero
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