You have a couple of other mistakes:
1) for one, looking at the bare output when doing parameter sweeps. In doing a temperature sweep this way you are missing the following:
1) DC offset vs temperature on all stages (clipping behaviour of the amp?)
2) Bias currents vs temperature on all stages (thermal stability of the amp)
3) Power dissipation vs temperature (and keep in mind you can dissipate less power the higher the temperature) for all stages
I'm sure there is more.
Doing a parameter sweep on resistors misses the point completely. Resistors are about the most stable component of all and the point of the design is to use that stability to dictate the stability of the whole amplifier, regardless of the tolerances of the other components. The real parameter you should be doing a sweep on is the one you cannot easily do a sweep on - transistor beta.
It seems you are trying to design a black box by measuring only the input and output variables of the black box - when designing a black box means you have to design what is IN it, and look at all the aspects of it's internal workings.
I have actualy put together a simple 4 transistor design that should do what you seem to want, but having read the 8 pages of this thread (so far) I have decided that either one of the following 3 is the case:
1) You are joking with us
2) You are unwilling to learn the basics
3) You are unable to learn the basics
In either case, putting up my design is of no help to anyone and just a further loss of time on my part, which is why this will be my last post in this thread.
1) for one, looking at the bare output when doing parameter sweeps. In doing a temperature sweep this way you are missing the following:
1) DC offset vs temperature on all stages (clipping behaviour of the amp?)
2) Bias currents vs temperature on all stages (thermal stability of the amp)
3) Power dissipation vs temperature (and keep in mind you can dissipate less power the higher the temperature) for all stages
I'm sure there is more.
Doing a parameter sweep on resistors misses the point completely. Resistors are about the most stable component of all and the point of the design is to use that stability to dictate the stability of the whole amplifier, regardless of the tolerances of the other components. The real parameter you should be doing a sweep on is the one you cannot easily do a sweep on - transistor beta.
It seems you are trying to design a black box by measuring only the input and output variables of the black box - when designing a black box means you have to design what is IN it, and look at all the aspects of it's internal workings.
I have actualy put together a simple 4 transistor design that should do what you seem to want, but having read the 8 pages of this thread (so far) I have decided that either one of the following 3 is the case:
1) You are joking with us
2) You are unwilling to learn the basics
3) You are unable to learn the basics
In either case, putting up my design is of no help to anyone and just a further loss of time on my part, which is why this will be my last post in this thread.
So when you first power this circuit on, I suppose U3,U4 will saturate until the charge on C5,C6 is established (as the effective time constant will be relativily slow). Is this why you use 1K emitter resistors to limit current? My guess is that the 1mF caps on the emitters of U3,U4 will cause them to explode. 
Won't the outputs become nonlinear when aproaching saturation without any neg. feedback? If efficiency is not what you are after with this class AB design, might as well go with class A.
Quite a sensitive bias for the outputs...they don't go into thermal runaway? You might consider a servo(Vbe multiplier) fed with current sources from + & - rails. Of course then would be more than 4 transistors.
Have you tried a resistor, maybe 50K from output to emitter of the MPSA18? Perhaps a 5K pot in series with a 10K resistor on that emitter...might help your DC output and you can lose C1. Even better if you could lose all the coupling caps, but this would be a redesign.
I know it can be frustrating but you must understand how to control the devices properly without letting any smoke get out.
It might work on a sim, but the real world can have more variables at work.
Won't the outputs become nonlinear when aproaching saturation without any neg. feedback? If efficiency is not what you are after with this class AB design, might as well go with class A.
Quite a sensitive bias for the outputs...they don't go into thermal runaway? You might consider a servo(Vbe multiplier) fed with current sources from + & - rails. Of course then would be more than 4 transistors.
Have you tried a resistor, maybe 50K from output to emitter of the MPSA18? Perhaps a 5K pot in series with a 10K resistor on that emitter...might help your DC output and you can lose C1. Even better if you could lose all the coupling caps, but this would be a redesign.
I know it can be frustrating but you must understand how to control the devices properly without letting any smoke get out.
It might work on a sim, but the real world can have more variables at work. CBS240 said:So when you first power this circuit on, I suppose U3,U4 will saturate until the charge on C5,C6 is established (as the effective time constant will be relativily slow). Is this why you use 1K emitter resistors to limit current? My guess is that the 1mF caps on the emitters of U3,U4 will cause them to explode.
Won't the outputs become nonlinear when aproaching saturation without any neg. feedback? If efficiency is not what you are after with this class AB design, might as well go with class A.
Quite a sensitive bias for the outputs...they don't go into thermal runaway? You might consider a servo(Vbe multiplier) fed with current sources from + & - rails. Of course then would be more than 4 transistors.
Have you tried a resistor, maybe 50K from output to emitter of the MPSA18? Perhaps a 5K pot in series with a 10K resistor on that emitter...might help your DC output and you can lose C1. Even better if you could lose all the coupling caps, but this would be a redesign.
I know it can be frustrating but you must understand how to control the devices properly without letting any smoke get out.
Well, first of all, U3, U4 do not saturate under any circunstances (at least my simulator is saying that). Second, the outputs are highly linear and are not insensitive. I don't know why everybody is saying that, I think it's because none has seen a circuit like this before; I'm saying man, I've made MJE betas go from 100..1500 and resistors go about +-50% variation on a parameter sweep simulation and nothing gone wrong. In fact, the circuit is very stable; I'll put here the plots for you analyse the results and tell me what you think.
PS: the feedback you proposed I've alredy done, but I didn't showed here the updated circuit yet.
Anyways, thakx for the post.
ashade said:
maybe people are still looking at your older circuit, not the latest one which due to the addition of those two feedback resistors is a huge improvement. all your assertions are right: U3/U4 aren't saturated, the circuit is highly linear and sensitive, and it is stable.
I think it has a chance to work in the real world now.
Oh, well, this is against better judgement, but here goes:
If you knew HOW and WHAT the simulator simulates, you would know why it is giving you that result. See what happens when you declare the initial voltage on those 1m and 200u capacitors as zero, which is what it will be at power-up. No amount of simulating will help if you keep simulating the wrong things or looking at just the results you are interested in.
Let me save you some time and tell you what happens at power up: capacitors present a short, which makes the B-E junctions of U3 and U4 in series directly from positive to negative power rail, which is for all intents and purposes a short circuit. What would be the base current here? Given infinite current from the power supply, on a real transistor given realistic Bbb'... oh, say, a couple of A? See what the datasheet for your U3 and U4 has to say about that - think they will survive? Even if they do, that base current will saturate C-E of U3 and U4 resulting in E-C + C-E being a short across the power supplies. Given realistic structure resistances, the current would be on the order of 10-15A. Even if this lasts only milliseconds, this is the result: both U3 and U4 go bang. See if you can solve that problem in your circuit. So, why didn't the simulator show that? Probably because you never asked it to simulate that.
Sure. Thanks for a good laugh there...
Apparently you think we 'unbelievers' are pulling cryticisms out of our hats (not to use another more appropriate term) just to anoy you. Engineering is about thinking up all sorts of crazy up-side-down preposterous things and getting them built, and working reliably, for years or more. Some of us have done it hundreds if not thousands of times, and do it every day for a living. How many have you? Think about it.
BTW having been in a teaching position regarding this subject, I can also tell you that your input stage would be grounds for immediate exam fail.
Really?
First of all, since the early 1950s you would be hard pressed to find a resistor that has more than +-10% tolerance, and maintains that over a sane temperature range (as in -50 to +150C). The only reason why it would get worse would be incompetence in selecting the right one. Doing a parameter sweep on resistors to figure out possible problems in your circuit and not finding problems is a good sign you do not know what you are doing. Have you tried sweeping one resistor one way, while the other goes another way? You must consider the several volts of offset in the input and output stage unproblematic, I guess. I know that I, and people that pay me to design for them, would not.
And about that beta sweep from 100 to 1500... at beta=100, the voltage across your 0.2 ohm resistors is about 19mV, so the bias current of the output is about 95mA, and the output stage idle power dissipation is about 2.87W. At beta=1500, the voltage across your 0.2 ohm resistors is .283V, and the bias current is 1.41A, giving a power dissipation of 41.67W from the output stage, at idle. Don't tell me you missed that one? It is fortunate that beta does not vary THAT much. Still, this would be pretty signifficant considering your amplifier can, ideally, output maybe 20W RMS at clipping. In a worst case scenario, with 1:2 beta differences, it will lose about 8V of headroom, and the output power will fall to only about 2W before clipping. That's of course if it ever gets past the exploding U3 and U4 problem. A topology that results in a 10-fold reduction of output power and double increase of power supply power with standard component tolerances, would not be very successful.
ashade said:
If you knew HOW and WHAT the simulator simulates, you would know why it is giving you that result. See what happens when you declare the initial voltage on those 1m and 200u capacitors as zero, which is what it will be at power-up. No amount of simulating will help if you keep simulating the wrong things or looking at just the results you are interested in.
Let me save you some time and tell you what happens at power up: capacitors present a short, which makes the B-E junctions of U3 and U4 in series directly from positive to negative power rail, which is for all intents and purposes a short circuit. What would be the base current here? Given infinite current from the power supply, on a real transistor given realistic Bbb'... oh, say, a couple of A? See what the datasheet for your U3 and U4 has to say about that - think they will survive? Even if they do, that base current will saturate C-E of U3 and U4 resulting in E-C + C-E being a short across the power supplies. Given realistic structure resistances, the current would be on the order of 10-15A. Even if this lasts only milliseconds, this is the result: both U3 and U4 go bang. See if you can solve that problem in your circuit. So, why didn't the simulator show that? Probably because you never asked it to simulate that.
Sure. Thanks for a good laugh there...
Apparently you think we 'unbelievers' are pulling cryticisms out of our hats (not to use another more appropriate term) just to anoy you. Engineering is about thinking up all sorts of crazy up-side-down preposterous things and getting them built, and working reliably, for years or more. Some of us have done it hundreds if not thousands of times, and do it every day for a living. How many have you? Think about it.
BTW having been in a teaching position regarding this subject, I can also tell you that your input stage would be grounds for immediate exam fail.
Really?
First of all, since the early 1950s you would be hard pressed to find a resistor that has more than +-10% tolerance, and maintains that over a sane temperature range (as in -50 to +150C). The only reason why it would get worse would be incompetence in selecting the right one. Doing a parameter sweep on resistors to figure out possible problems in your circuit and not finding problems is a good sign you do not know what you are doing. Have you tried sweeping one resistor one way, while the other goes another way? You must consider the several volts of offset in the input and output stage unproblematic, I guess. I know that I, and people that pay me to design for them, would not.
And about that beta sweep from 100 to 1500... at beta=100, the voltage across your 0.2 ohm resistors is about 19mV, so the bias current of the output is about 95mA, and the output stage idle power dissipation is about 2.87W. At beta=1500, the voltage across your 0.2 ohm resistors is .283V, and the bias current is 1.41A, giving a power dissipation of 41.67W from the output stage, at idle. Don't tell me you missed that one? It is fortunate that beta does not vary THAT much. Still, this would be pretty signifficant considering your amplifier can, ideally, output maybe 20W RMS at clipping. In a worst case scenario, with 1:2 beta differences, it will lose about 8V of headroom, and the output power will fall to only about 2W before clipping. That's of course if it ever gets past the exploding U3 and U4 problem. A topology that results in a 10-fold reduction of output power and double increase of power supply power with standard component tolerances, would not be very successful.
Don't worry Jan, I wasn't really writing it for his benefit, plus I'm more amused than excited.
On a related note, it would be interesting to see what people come up with, being limited to say 5 transistors (darlingtons count as two, MOSFETs and JFETs are permitted, diodes are not limited in number)...
On a related note, it would be interesting to see what people come up with, being limited to say 5 transistors (darlingtons count as two, MOSFETs and JFETs are permitted, diodes are not limited in number)...
Hi Ilmzin,
nice to see you back in this thread!
Actually I am allready off this thread, but thought I could make a last visit.
As for the sc. "competition", it would have been fun, but I don't think this too much downgraded thread is worth it anymore the attitude shown by some "aspirants", maybe later, maybe somewhere else my friend.
With 5 transistors, I can "show" at least so much what I would have probably done, with only words: Diff pair, bootstraped VAS, Push-Pull.
Au revoir, Michael
nice to see you back in this thread!
Actually I am allready off this thread, but thought I could make a last visit.
As for the sc. "competition", it would have been fun, but I don't think this too much downgraded thread is worth it anymore the attitude shown by some "aspirants", maybe later, maybe somewhere else my friend.
With 5 transistors, I can "show" at least so much what I would have probably done, with only words: Diff pair, bootstraped VAS, Push-Pull.
Au revoir, Michael
Great now at least they will contain thier smoke U3,U4 will still saturate until C5 C6 fill up with charge. The 1K's will keep them from exploding. C5,C6 is your problem. Get rid of them and choose another biasing technique. Why use 2 transistors for the VAS? 1 will do fine. Use the other as bootstrap(current source). Input on base of MPSA18, use this collector to drive U3. U4 as current source. Need a collector resistor on the MPSA18 though. Take neg feedback from collector of U3/U4 to the emitter of the MPSA18 with resistor, use a pot in series with resistor combined as the emitter resistor of the mpsa18 for DC control. Just an idea...
ilimzn, I also am amused with this thread...
U3,U4 will still saturate until C5 C6 fill up with charge. The 1K's will keep them from exploding. C5,C6 is your problem. Get rid of them and choose another biasing technique. Why use 2 transistors for the VAS? 1 will do fine. Use the other as bootstrap(current source). Input on base of MPSA18, use this collector to drive U3. U4 as current source. Need a collector resistor on the MPSA18 though. Take neg feedback from collector of U3/U4 to the emitter of the MPSA18 with resistor, use a pot in series with resistor combined as the emitter resistor of the mpsa18 for DC control. Just an idea...ilimzn, I also am amused with this thread...
Ultima Thule said:
Of course, and I'm assumind diodes as bias servo - sounds good. Needs good output transistors (high beta). Same output configuration with single ended input needs only 4 transistors but requires AC input coupling.
It actually gets quite usable with a MOSFET output stage, though to really do it right you have to 'waste' one transistor as the bias generator, so no more LTP input. But you can make it rail to rail with one cap and one resistor more
and even have full output with about 25mV at input, at about 1% distortion.
ashade said:
At power on there is no voltage across C5 or C6, right? That means the +-15 Volts must be spent across R2-U3be-U4be-R1. Given that Vbe is generally 0.6 volts, there will be 14.4 volts across R2 and R1 respectively. That leaves only 0.6 volts for Vce, i.e saturation.
Not that it matters much; eventually C5 and C6 will charge, and nothing will blow up in the process in this particular case. It's just something that you need to understand; sooner or later you'll be faced with a situation where it does matter...
Rune
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