Thermal considerations for Fairchild SDIP bridge rectifiers

[Mark Johnson]

20 * log10(1 / (gm * r0))

20 * log10(1 / (0.917 * 608))

20 * log10(1/557)

20 * -2.746

-54.9 dB

===========================

The curve has three segments; it takes 4 numbers to describe these. The numbers that immediately pop into mind, are simply the coordinates of the four endpoints of the three straight lines:

• The height (magnitude) of the shelf on the left
• The height (magnitude) of the shelf on the right
• The frequency of the corner on the left
• The frequency of the corner on the right

Unfortunately, this formulation allows for any and every possible slope of the middle segment, whereas real circuits made from real components only have slopes that are integer multiples of 20dB/decade.

The four numbers which define this particular shape are:

• The height of the shelf on the right (-54.9dB)
• The height of the shelf on the left (0dB)
• The slope of the middle portion (+20dB/decade)
• The upper corner frequency (163 MHz)

If you want to know the lower corner frequency, you can calculate it from the upper corner frequency, the slope, and the difference in height of the two shelves.

You can calculate the upper corner frequency quite readily: it's (1 / (2 * pi * Ccb * Roa)):

1 / (2 * 3.1416 * 1.24E-10 * 8.0)

1 / 6.233E-9

1.60E8 = 160 MHz.

 

[Mark Johnson]

And using Bob Cordell's favorite analysis tool "re" (the effective resistance in the emitter circuit; re = 1/gm), we observe that the low frequency attenuation is the result of a simple two-resistor voltage divider.

The output connects to the input via resistor Ro (608 ohms). The output connects to the perfect, pure, ripple free DC voltage on the emitter (which follows the base, which is a perfect pure ripple free DC voltage) via the Cordell emitter series resistor re = 1/gm = (1/0.917) = 1.091 ohms.

What's the attenuation of a voltage divider with 608 ohms on top and 1.091 ohms on bottom? Vout/Vin = 1.79E-3 = -54.9dB.

Thank you Bob Cordell.

Furthermore we realize that the attenuation would grow and grow if Ro got larger and larger. Since Ro is caused by Early voltage (Ic vs Vc curves that slope upwards), we now have a reason to seek out transistor types for our emitter followers, with high Early voltage. Even better, a cascode circuit which gives virtually infinite Early voltage and thus, virtually infinite attenuation at low frequencies. Oh by the way: two series pass regulators, one after the other, are effectively, a cascode.

Boy this theory stuff is useful.

 

[SGK]

Useful indeed when it is explained well and in detail. Does everyone know this stuff except me?

The Ro connection was easier for me to get. I was struggling with the other half of the divider. From Cordell I had "the transistor will act as if a change in its base-emitter voltage is directly impressed across [re]" and that re=1/gm. But that wasn't enough for the penny to drop here. When looking for the 'path to ground' via the base I was struggling with what do to with Rpi (which also connects Emitter to Base), Roa of 8R and the difference between Vopamp and ground. Plus there is the fact that current doesn't flow into the base from the collector. I guess I was getting very tangled between 'large signal' and 'small signal' thinking. I was also fixated to an extent on finding the lower corner frequency as a point whereby the impedance of a capacitor had lowered enough for signal at the collector to take a different path to the output than over Ro.

I find it somewhat odd that one can find numerous tutorials online with respect to emitter follower regulators, but not one that I found went through the small signal dynamics and underlying operation. Also, while I know Bob placed a caveat right at the beginning of that chapter, it would certainly benefit, in my view, from a little more detail or being a little more verbose in places.

This has been an extremely helpful tutorial for me. I hope it is of value to others as well. Thanks again.

 

[Mark Johnson]

Engineering education teaches you to perform the analysis yourself (using mathematics). If you hope that every possible engineering analysis might be published in at least one book, somewhere, complete with helpful step-by-step explanations in English instead of mathematics, you may find yourself disappointed.

Chefs invent new dishes. Cooks write recipes based on their educated guesses about what a chef probably did. Moms follow recipes. Each of these job titles requires a different level of insight.

 

[SGK]

Well I think I have learnt a lot, albeit slowly.

Hopefully I will get the revised boards tomorrow.

With regard to the former discussion about the op amp by-pass caps, I found the comment here interesting: Walt simply dropped the by-pass caps altogether when moving the supply from Vin to Vout with the 'Jung 2000 regulator'.

 

[SGK]

Initial transient/stability tests of Darlington config (D44VH10 pass; MMBT6429 driver) seem good. Long tail with 'load on' has gone. Compare with former Sziklai board results in post 223. No signs of instability that I can see. Residual wobbles likely just test setup. I used 16 sample averaging. Resistors R25, R31 and R44 are all just 0 Ohm jumpers. C15 and C17 are populated. 18V DC input at R3 from bench supply. R10 set such that Vin to the D44VH10 is 16V. 12V output. (CY1 not populated.)

I have some PMBT6428,215 MMBTH10 and MMBT2369A to try, as well as some 2SC6144SG.

 

[Mark Johnson]

Looks very stable, congratulations! Sort of annoying that the regulated output bumps ~ 200mV during the transient ; I imagine simulation predicts less than 200mV. You could slow down the edge rate by temporarily tack-soldering a 2.2nF capacitor across the drain-to-gate slowdown capacitor C6 of your transient load stimulator PCB. Hopefully this will give a ~ 350 nanosecond fall time on the MOSFET drain and thus a 350 nsec risetime/falltime of the load current -- the same risetime/falltime as a 1 MHz sinewave. (My wild guess that 2.2nF produces 350ns fall time is just that, a guess; experiment to find the correct value).

The big idea is that class B and class AB amplifiers draw half-sinewave currents from their supplies, and these asymmetric current waveforms with discontinuous slope @ crossover, have Fourier components that extend to many many harmonics above 20 kHz. By choosing a risetime consistent with 1 MHz you're stimulating the 50th harmonic (!!) which ought to be plenty more than enough even for the most cautious experimenters. Good ole Jan Didden is happy with a lot less. Maybe the regulated output bumps a lot less when the load current waveform's risetime/falltime is 350 nsec.

edit- Might give extra peace of mind to view the output of the NSC/TI preregulator IC during full speed transient load testing. Just to be sure that it's not making life hell for your downstream discrete circuitry.

 

[SGK]

Hi. Sim is about 50mV (0.1A->0.6A). I took a look at probing the pre-reg output capacitor. The responsiveness of the pre-reg seems awful (first two pics probe the pre-reg output cap pins).

Probing C9's pins required me to turn everything upside down and I suspect much of the overshoot shown above is test setup/how I am probing. This is because I also probed the output, but now at the underside of the output connector (second two pics). The initial overshoot is significantly lower. Flip it all back over, probe as before which was where I have soldered the wires from the output connector to the chop-chop box and I get the results I had before.

The last pic shows the results from probing the pins of the two output cap closest to the output connector. I suspect for this sort of test this is where I ought to be probing yet the actual output of the reg board is where the connector pins come together - topside...

PS: I don't have a 2.2nF cap on hand and will have to source one in order to try the test you suggested although it may be redundant given the foregoing.

 

[Mark Johnson]

I dunno, your measurements for this Load transient, are a lot better than TI's datasheet Figure 8 promises. Probably because you are setting C9 = 220uF rather than their puny 22uF. (And also, your output capacitors C21 C23 absorb some of the blunt force trauma of the load step, so the preregulator chip sees a less aggressive current waveform).

A glance at datasheet Figure 13 suggests that you have exactly split the middle of the logarithmic plot by choosing R15 = 0.3 ohms. In retrospect was that too conservative? Maybe do you want to try R15=(0.12R - CapacitorESRrating) ohms instead, to see how much better your Load transient becomes? See "words.png" 2nd attachment below.

_

 

[SGK]

Hi. I have some 0.1R resistors coming, possibly today, which I can try. I don't have anything smaller.

The capacitor I used is this one: 647-UKL1V221KPD. I wish I had an LCR meter to measure its series resistance more directly. From the data sheet, at 120Hz the tangent of loss angle is 0.12 and I understand ESR = tan x Xc. The reactance of a 220uF capacitor at 120Hz is 6 Ohms. So I have an estimated ESR of 0.7R.

Therefore, if I have done my calculations correctly, a 0.3R series resistor places things right at the maximum mentioned in the excerpt you posted above. It also suggests that replacing R15 with a zero Ohm jumper may well be an option worth trying.

 

[SGK]

It also suggests that replacing R15 with a zero Ohm jumper may well be an option worth trying.

Hmm. Doesn't look from the attached that this is the right answer. Initial overshoot at output of the pre-reg is less but overall error seems greater. First three probing C9. Rest probing output cap C23.

 

[SGK]

Same measurements but with 0.1R for R16

 

[SGK]

If you're feeling adventurous you could think about using a super high fT device for the initial emitter follower: MPSH10(TH)/MMBTH10(SMD) , 2N5770(TH) , 2SC4082(SMD) , PMBT6428(SMD) , PN2369A(TH)/PSMT2369(SMD) , and so on. Thanks to the modest output current of your regulator, and thanks to the beta of the output transistor, the emitter current of the initial EF can be quite modest. And as long as you pick a device with a common pinout, you'll be able to yank it off the board and replace it with something more orthodox / less frightening, at the first sign of unexpected behavior.

Perhaps time to try something adventurous. I purchased 10 each of:

MMBTH10 - data sheet provides an fT of 650MHz minimum
PMBT6428,215 - NXP's data sheet provides an fT of 100-700MHz i.e. the same as On Semi's MMBT6429LT1G
MMBT2369A - Fairchild's data sheet doesn't provide an fT figure

(Perhaps I should have picked up some 15GN03CA-TB-E with an fT of 1-1.5GHz.)

I think I will try the MMBTH10 and check for stability.

EDIT: seems stable

 

[Mark Johnson]

2N2369 is a presupplied device model with LTSPICE so you can look up its simulated forward transit time (model parameter TF) and from that, calculate its fT. See Figure 1. I get fT=700 MHz; you should double check my arithmetic.

Octopart.com has ST Microelectronics' datasheet for the 2369 in an old metal can thru-hole package (here). It says 500-675 MHz.

I own several LCR meters which will also measure ESR of big electrolytic capacitors, including this one from HP/Agilent/Keysight and also the hobbyist favorite DE-5000 sold on Amazon, eBay, etc. I love them to death. But if I had no meter I would spend USD 0.36 to buy a new capacitor with factory spec'd low ESR and thereby avoid spending $100-300 on a meter.

The ESY series of low-Z capacitors from Kemet includes ESY227M050AH2AA which is 220uF, 50V, 0.042 ohms ESR, 1.37 amps ripple current. Same lead spacing and same diameter as the capacitor you're currently using, but 6.5mm shorter. See Figure 2. Drop it in and play with series resistors to your heart's content. OR, as long as you're buying a new capacitor anyway, consider a low-ESR cap with more microfarads.

The ESC477M035AH4AA is 470uF, 35V, 0.039 ohms ESR, 1.04 amps ripple current, same footprint as your cap but 3.5mm shorter.

Hmmm, suppose the preregulator is infinitely slow to respond to a change in load current deltaI. Then the voltage change on the preregulator output is just (deltaI * (R3+ESR)) and then the monstrous cap prevents any further voltage change. If we plug in deltaI = 500mA = 0.5 amps, it kinda resembles the measured voltage changes. Hmmm.

_

 

[SGK]

Thanks for the heads re the supplied model for the 2N2369. Yes, I calculated 699 MHz, call it 700, also. Incidentally, the 2N2369 doesn't model quite as well as the MMBT6429 from a line rejection perspective and neither actually does the MMBTH10.

Thanks for the cap suggestions. I will add them to my next Mouser order.

I'm not sure I follow the last point. R3?

 

[Mark Johnson]

Oops I mean the resistor in series with the electrolytic cap at the preregulator output node: R15 & R16. When the load current suddenly changes, (deltaI * (ESR+R15)) volts appears across this resistor, so perhaps the preregulator output node changes by (deltaI * (ESR+R15)) too? You can't change deltaI but you can change (ESR+R15).

 

[SGK]

So minimise ESR+R15 subject to stability criteria.

I guess my calculation in post 310 was way off? If I do the same calc for the 220uF Kemet cap you listed above I'd still get 600mR.
Tan % = ESR/Xc
ESR = Tan % * Xc
Tan % @ 120Hz = 0.1
0.1 * (1/(2*Pi*f*C))
0.1 * (1/(2*Pi*120*220u)

Bears no relation to the impedance figure at 100kHz so must be wrong...

 

[Mark Johnson]

I guess there must be somebody who really cares about ESR or Dissipation Factor, at 120 Hz. So capacitor makers specify tan_delta at 120Hz. On the other hand, what us power supply decoupling folks want to know is: what's the series resistance at really high frequencies? So they measure ESR again at 100 kHz and spec that.

Perhaps 120Hz is below the knee frequency where the ESR curve bends up sharply (attached). I don't personally know.

_

 

[SGK]

Ah I didn't realise there was a knee to the ESR plot - I had thought it simply a straight, horizontal line. Thanks.

FWIW here are some model plots of line rejection for each of D44VH10 and 2SC6144SG pass transistors and drivers MMBT6429 and MMBTH10. I haven't tried dropping in a 2SC6144SG and subjecting it to transient testing yet but I will try to. It's a shame I don't really have what's required to test the actual line rejection.

 

[Mark Johnson]

I don't imagine the external consultants who built those SPICE models for NXP, Motorola, Fairchild, Sanyo et al, were trying for 1 PPM (120dB) fitting accuracy. Nor do I imagine they achieved 1 PPM whether they were trying or not. So I don't personally believe SPICE is necessarily the last word in which-transistor-performs-best-in-my-120dB-circuit. You've got the real transistors, why not plop them down and try whatever tests you are able to apply. Maybe there will be differences, maybe one will be noticeably better than the others. Or one may be worse than the rest.

John Walton's article in Linear Audio Volume 4 used "Walt Jung's Rail Driver" to inject known waveforms on top of the raw +25VDC input. I expect these are Figure 6 and Figure 5 of Walt's article in Audio Amateur. Maybe that's your next project.

Off topic, I had a thought about electrolytic capacitor datasheets. Maybe Dissipation Factor is measured at 120 Hz because people actually want to calculate ... drum roll ... power dissipation in their capacitors. They calculate ESR_120Hz = DF * (1/(2*pi*120*C)) and then use that number in an LTSPICE simulation of their circuit design. Plot the power-vs-time curve {LTSPICE thermometer icon} of component ESR_120Hz and note its peak value. Tell LTSPICE to calculate the average and RMS average of its dissipation over one complete cycle of the AC mains. If power dissipation in the capacitor is uncomfortably large, select a bigger capacitor with lower DF*Xc and simulate again.

I found another plot in a Vishay app note, showing that ESR rises at low frequencies (dotted lines). Illinois Capacitor isn't the only company who says so.

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