Thermal considerations for Fairchild SDIP bridge rectifiers

[SGK]

Duh I was thinking you were talking about an inherent difference between the D44VH10 versus D45VH10.

Re the fT of the driver, I was thinking in a much more basic, 'mechanical' sense. In the Teddy Pardo-resistor-to-GND variant the driver can only influence Vout via the Vbe of the pass transistor. To abuse the Art of Electronics cartoon, the driver is a superfast, lightweight guy trying to get pass 'transistor man' to react faster. The driver can be as fast as lightning but heavyweight transistor man still has to do the work/regulation. But I will pick up a few of the higher fT devices and dabble.

Speaking of the 'resistor to GND' I'm suddenly doubting myself on the -ve side of the reg. I think it should still go to GND rather than V- (for the same resistor value and target current as the +ve side of the reg).

 

[AndrewT]

the GND in each half of the diagram is with reference to that half daigram.
For the upper the GND is it's -ve rail i.e. global Zero Volts.#For the lower half of the diagram the GND is to the -ve rail this time that is the global -ve rail.

The same applies to all the other GND in the upper and lower halves, except the one GND that is purely capacitively coupled. It can go to any rail that has low impedance to the local ground. This cap coupled GND is for the local supply rail decoupling of the opamp. it would probably be better to take that straight to pin4 of it's opamp.

 

[SGK]

You are right.

Taking the low side of the bypass caps to op amp pin 4 is rather challenging given my layout. But the distance between the two is minimal and both GND and V- are planes and so I suspect it is little issue.

 

[SGK]

If you're feeling adventurous you could think about using a super high fT device for the initial emitter follower: MPSH10(TH)/MMBTH10(SMD) , 2N5770(TH) , 2SC4082(SMD) , PMBT6428(SMD) , PN2369A(TH)/PSMT2369(SMD) , and so on.

I'm going to order a few MMBTH10, PMBT6428 and MMBT2369A.

The 2SC4082 don't appear to come in SOT-23 and I believe the MMBT2369A is the current SMD equivalent for the PN2369A.

All seem pin compatible in SOT-23.

 

[Mark Johnson]

NJD1718 SMD power transistor has fT=80 MHz, higher than D45H11.

2SA6144 thru hole power transistor has fT=330 MHz, higher than D45H11.

Those are PNPs; you might want to have a look at the NPNs too.

 

[SGK]

On Semi provide a Spice .subcircuit for the 2SC6144SG. (It would appear to require a correction to the pin order of the Q1 line to work.) It doesn't model well when simply dropped into the existing circuit in lieu of the 50MHz D44VH10G. Line rejection is a few dB worse and phase/gain margins and transient response are also worse suggesting the need for a small compensation cap which worsens modelled line rejection further still.

We have a 50MHz GBP op amp driving a c400MHz fT driver transistor which in turn is driving either a 50MHz or a 330MHz fT pass transistor. Intuitively I would have thought the op amp a bottleneck in terms of this 'speed' when stepping to the higher fT pass transistor. (Quite ignoring modelled line rejection even at 1MHz is already 109dB with the D44VH10G.) Presumably this applies to higher fT driver transistors as well.

 

[Mark Johnson]

How many degrees of phase shift do you see from opamp output pin to regulated output voltage? (Use a two-point differential probe in LTSPICE). That's the contribution of the supposedly blinding fast pass transistors and the level shifter and any base stopper resistors you may have included. Perhaps this total phase shift is less than one degree at frequencies where you really care a lot. Perhaps it is shockingly higher than one degree and is actively destroying your phase margin. It's a number I assume you already know.

You could find the SPICE model parameter which encapsulates fT and .STEP the value of that parameter in simulation, temporarily pretending that you are the discrete transistor fab wizard of space and time, who can make transistors as fast or as slow as desired, just by snapping your fingers. This stepped simulation lets you simply see how much better (or how little better) it all gets when you increase or decrease fT. Now you'll know quantitatively whether the fT design "knob" has a large impact or a small impact. And you didn't have to trust anybody else's opinion to find it out; you relied on your own pluck and ingenuity and your own resourcefulness.

example

 

[SGK]

How many degrees of phase shift do you see from opamp output pin to regulated output voltage? (Use a two-point differential probe in LTSPICE). That's the contribution of the supposedly blinding fast pass transistors and the level shifter and any base stopper resistors you may have included. Perhaps this total phase shift is less than one degree at frequencies where you really care a lot. Perhaps it is shockingly higher than one degree and is actively destroying your phase margin. It's a number I assume you already know.

Ugh you are probing a knowledge gap which I know you know I am uncomfortable with. I understand that poles and zeros in a circuit cause phase shift and that when phase shifts total 180 degrees for a frequency where we are still applying gain then we have positive feedback and oscillation. (The phase shift means that the sample of the output fed into the amplifier's inverting pin is actually added to the input, thereby reinforcing the error and the situation compounds). I understand we desire good margin from both a gain and phase perspective in models as there are undoubtedly poles and zeros in the actual circuit which aren't accounted for in our models. (I also understand the amount of phase margin is directly related to damping factor in a second order linear system.) I know how to plot loop gain and phase margin in LTspice (pic 1).

That's about where my knowledge ends. For this circuit I see phase margin of about 90 degrees and about 40dB or so of gain margin (pic 2). I have never understood the relationship between this bode plot's phase and the phase shift shown if I simply plot Vout for the circuit with AC=1 in its source voltage (rather than the separate AC stimulus injection used for the loop gain and margin analysis) and have always selected "Don't Plot Phase" there.

If I plot the difference between Vout and the output of the op amp in my line rejection analysis circuit I get pic 3.

You could find the SPICE model parameter which encapsulates fT and .STEP the value of that parameter in simulation, temporarily pretending that you are the discrete transistor fab wizard of space and time, who can make transistors as fast or as slow as desired, just by snapping your fingers. This stepped simulation lets you simply see how much better (or how little better) it all gets when you increase or decrease fT. Now you'll know quantitatively whether the fT design "knob" has a large impact or a small impact. And you didn't have to trust anybody else's opinion to find it out; you relied on your own pluck and ingenuity and your own resourcefulness.

example

I understand the principle of what you did here, but I can't get FT to step in my circuit. I see the variable TF defined in the D44VH10 .model statement:

TF=2.84126e-09

(which incidentally seems to imply an FT of 56MHz rather than 50MHz but whatever.) In prior modelling I have used the 'value' fields in a circuit device (CTRL left click on the device on a Mac) to override the values in the included .model statement and redefine them as variables that can then be defined freely or stepped with Spice directives in the circuit. (Example: if CoilRes was set to 650 in the .model statement then use the value line to set CoilRes={Rcoil} and then stepping Rcoil.) I ought to be able to simply redefine TF as a formula in one of the Value fields and then .param step the variable FT within that formula in a separate Spice statement on the schematic. But it doesn't work. I've also tried, as you did, redefining TF as the variable {TAU_F} in the .model file included via the .inc command and then providing a formula for TAU_F with a Spice directive on the circuit. But I still can't get it to step (with all manner of combinations of curly versus regular parentheses). Hints appreciated.

.param TAU_F={1/(6.283*FT)}
.param FT=55Mega
.step param FT list 55Mega 1Giga

 

[Mark Johnson]

Oscillation occurs when gain>1 and phase=360 degrees.

Since the control loop includes the opamp output and its inverting input terminal, the inversion contributes 180 degrees of phase shift. You want all the other phase shifts in the loop to add up to a total that's less than 180 degrees or else oscillation is guaranteed.

How much less than 180 degrees? "Phase Margin" less.

Textbooks warn that you need at least Phase Margin = 45 degrees to make sure the control system is stable in the presence of perturbations. Me, I prefer Phase Margin = 65 degrees if possible, but let's stick with the textbooks for now.

Using the textbook recommendation, the phase shift thru the opamp (including the inversion!), plus the phase shift thru the level shifter, plus the phase shift thru the output transistors & base stopper resistors, plus the phase shift thru the feedback divider, should be less than 315 degrees.

I'm suggesting you measure and tabulate each individual component of this summation. Then I'm suggesting that you use your yellow highlighter pen to direct your attention to the (pass transistor & base stopper resistor) line item. What is its contribution to total phase shift?

In a perfect world, all phase shift would come from the opamp pooping out near its GBW frequency. Ideally the phase shift of the feedback divider would be zero. The phase shift of the DC level shifter circuit would be zero. The phase shift of the (output transistors and base stoppers) would be zero. Then the bandwidth of the complete regulator loop, would be equal to the bandwidth of the opamp -- in your case, 50 MHz.

However, yours is not an ideal world. Each of the non-opamp circuits has, regrettably, positive nonzero phase shift. Some of them are easier to modify than others. I'm suggesting that you analyze whether the output transistors + base stoppers are a significant, or insignificant, contributor to the total phase shift. If you decide they are significant, I'm suggesting that you analyze whether different transistor fT parameters, do or do not make a noteworthy difference.

You may be able to debug your simulation problems by building a small toy circuit with six or fewer components, and trying to modify, jigger, and .STEP fT in that toy circuit. When you succeed, transfer the learning to your larger and more ambitions simulation. If you don't succeed perhaps you can exactly replicate the example circuit mentioned above. If that doesn't succeed perhaps Helmut Sennewald and company will debug your circuit for you at no cost.

 

[SGK]

Oscillation occurs when gain>1 and phase=360 degrees.

Since the control loop includes the opamp output and its inverting input terminal, the inversion contributes 180 degrees of phase shift. You want all the other phase shifts in the loop to add up to a total that's less than 180 degrees or else oscillation is guaranteed.

Yes. My post was imprecise.

You may be able to debug your simulation problems

I've got this fixed. For some unknown reason I started having a lot of problems with my .asc file. .INC statements that had worked previously simply stopped working etc. I decided to build a new schematic in a new file from scratch. Stepping ft now works. (I can no longer get the old asc to work at all. I can only think that things got corrupted somehow.) In the interim I updated my LTspice software and did a model update. Oddly, the Bode plot looks even less correct below 1kHz although it produces about the same UGF and phase/gain margin. See below - pic 1 meant to replicate the bode plot above and pic 2 steps the pass transistor ft 56Mz and 1GHz. Pics 3 and 4 show the difference in transient response.

I'm suggesting you measure and tabulate each individual component of this summation. Then I'm suggesting that you use your yellow highlighter pen to direct your attention to the (pass transistor & base stopper resistor) line item. What is its contribution to total phase shift?

In a perfect world, all phase shift would come from the opamp pooping out near its GBW frequency. Ideally the phase shift of the feedback divider would be zero. The phase shift of the DC level shifter circuit would be zero. The phase shift of the (output transistors and base stoppers) would be zero. Then the bandwidth of the complete regulator loop, would be equal to the bandwidth of the opamp -- in your case, 50 MHz.

I understand.

I did some more work here, but want to spend more time with it.

That last sentence helped the penny to drop. It now seems stunningly obvious.

 

[Mark Johnson]

I have sometimes wondered whether it would be worth the hassle to install Apache Subversion, a free and widely used source code control & revision system. Then it becomes trivially easy to roll back to any of the earlier revisions, in case a LTSPICE .asc file suddenly stops working, or a KiCad PCB schematic/layout explodes, or ...

It's free, it's well-tested and thoroughly debugged, and it's relied upon by software guys who make 20 or 100 revision check-ins per day. Why not me too? Answer: lethargy, indolence, torpor.

The government doesn't put up a traffic light at an intersection until somebody dies there in an accident. I spoze I'm waiting for a fatal accident before installing Subversion.

 

[SGK]

Eventually I found the problem with my original file. When I tried dropping in the 2SC6144SG, rather than using a .inc statement I simply pasted the .subckt Spice directive directly onto the schematic. Although I've no idea why, and even though I am no longer calling on this sub circuit anywhere in the schematic anymore, unless the .subckt Spice directive is turned into a comment I get a missing model error in relation to the Qd44vh10 even though there is a clear .inc statement for this model. Go figure.

(Also, I found what was causing the difference in behaviour below 1kHz or so. That, at least, was a silly mistake on my part.)

Back to examining phase margin...

PS: Apple's OS has Time Machine built in. It does hourly backups. Can come in handy.

 

[SGK]

A tentative answer.

I found I could not simply use a differential probe. The phase plot presented didn't make sense. I needed to label nets and plot V(A)/V(B) to find the impact to phase margin from node A versus node B. (I later confirmed that this was indeed correct by asking on the LTspice Yahoo forum.)

I believe the attached is a fair analysis and submit it for review/criticism. Pic 1 is the circuit with relevant nodes labelled. Pic 2 shows the composition of phase margin degradation. The blue trace is the phase margin for the circuit as a whole. At UGF of 1.34MHz there's 89 degrees of modelled phase margin. The red trace shows, as expected, that there's no phase shift caused by the level shift. The turquoise trace shows a small boost to phase margin at UGF from the driver transistor. This small boost is pretty much cancelled by the pass transistor: magenta trace. (The grey trace shows the impact to phase margin from the feedback resistor network - it's only significant at very high frequencies and I assume it results from modelling the impact of default parasitic properties.) The real issue would appear to be the degradation in phase margin caused by the op amp. I believe that in a perfect world - with a perfect op amp - one would expect the green trace to simply be a straight line at 180 degrees, i.e. the op amp degrades phase by a flat 180 degrees thereby leaving a phase margin of 180 degrees at the UGF. It doesn't, but rather degrades phase margin to 89 degrees or so at UGF.

EDIT: of course we can also look at the AD817 data sheet Fig 10 to see the phase margin of the op amp and compare it with the green trace. Pic 3. Perhaps unsurprisingly the green trace isn't that far off the data sheet. So perhaps more importantly I need to identify the cause of the rolloff in phase margin beyond the UGF...

I've also been playing around with the output caps. I can see how the output cap capacitance interacts with the pass transistor to create a pole. (Pole Po in the article here which you provide in the Super Reg thread.) Lower the capacitance and, all else being equal, the pole shifts higher in frequency and provides more loop gain as a result. (Similarly one can play around with the ESR zero.) The thing I find odd, however, is that an identical change in the circuit used to model line rejection (identical except for no breaking of the feedback loop and AC stimulus comes from the input voltage- voltage out is probed in dB) does not show any benefit from the higher loop gain at the frequencies at which it changed. I would expect better line rejection with higher loop gain at any given freq (where loop gain is positive).

 

[SGK]

I got timed out editing the above post. I would alter the last sentence in my edit paragraph to:

So perhaps more importantly I need to identify the cause of the rolloff in phase margin beyond the UGF as there's at least of 10 MHz of decent margin out of the op amp and the pass transistor (and other components measured thus far) would seem to assist margin.

 

[Mark Johnson]

Good-o.

Don't forget that the feedback divider (12V in, 6.9V out) drops the whole overall entire frequency response plot by a factor of about 2. So your 50 MHz opamp can give, at best, 28 MHz GBW in a loop with a feedback divider.

This is why Linear Technology (re)invented the Absolute Current Source Reference topology for their latest voltage regulators: continuously adjustable output voltage with NO feedback divider and NO reduction of loop bandwidth.

 

[SGK]

I've also been playing around with the output caps. I can see how the output cap capacitance interacts with the pass transistor to create a pole. (Pole Po in the article here which you provide in the Super Reg thread.) Lower the capacitance and, all else being equal, the pole shifts higher in frequency and provides more loop gain as a result. (Similarly one can play around with the ESR zero.) The thing I find odd, however, is that an identical change in the circuit used to model line rejection (identical except for no breaking of the feedback loop and AC stimulus comes from the input voltage- voltage out is probed in dB) does not show any benefit from the higher loop gain at the frequencies at which it changed. I would expect better line rejection with higher loop gain at any given freq (where loop gain is positive).

Here I step Cout from 470u->220u->100u->47u. The pole shifts higher in frequency creating more loop gain between 100Hz and 100kHz. Phase and gain margin remain relatively static. I'm surprised to see no change in line rejection from the extra loop gain available for error correction. There's also no change to output impedance or transient response with varying Cout which isn't my recollection from modelling the MOSFET pass transistor configuration.

 

[SGK]

Don't forget that the feedback divider (12V in, 6.9V out) drops the whole overall entire frequency response plot by a factor of about 2. So your 50 MHz opamp can give, at best, 28 MHz GBW in a loop with a feedback divider.

Yes I was looking at that late last night. I understand... The AD817 data sheet plots Open Loop Gain. The amount of gain available for error correction in the closed loop response is AOLB. 1/B here (below about 20MHz above which parasitics become more influential) is a relatively simple 4.8dB or so. LTspice plots Loop Gain AOLB directly and so we ought to see a lower level of gain (4.8dB lower) at low frequencies than the open loop gain in the data sheet (were we to have a perfect model and the same supply range as the data sheet). Then there are other factors affecting the loop gain response of the circuit beyond just the op amp, not the least being the pole created by the interaction of the pass transistor and output capacitance.

Here's what I was chewing on last night and still don't get. If Loop Gain is the gain available for error correction and I can view this circuit as two parts (A) an RCRC network and (B) the error correction or control feedback network, why does the line rejection plot not equal the line rejection from A (see plot of Vin_Pass) plus the loop gain from the Bode plot? And how can line rejection beyond the UGF (where loop gain, the gain available for error correction, is 0dB) be any more than just that from the RCRC network? I'm missing something basic here.

 

[Mark Johnson]

Maybe if you built side by side simulations of (the whole circuit) and (the whole circuit but element X replaced by an ideal perfect X) you could find out who is doing what.

See what happens to the loop gain plot and the ripple rejection plot, when you

• set R1=R2=0.001R, C2=C3=0.001pF
• replace Q1-Q2-J1 with an ideal 8.0mA current source
• replace U1 with an ideal 5.0V voltage source
• replace D1 with an ideal 6.9V voltage source
• delete R9-C5-C6 (they filter the output!) and feed U2 from an ideal 12V source
• replace U2 with a UniversalOpamp2 set to have the same Av0 and GBW and SR and PM

 

[SGK]

Good strategy. Thanks for the reminder.

AvO? Help in the Mac version of LTspice sucks. I cannot find anywhere how to set the variables for the UniversalOpamp2. I suspect the ones you listed are just that but I was puzzled by AvO. Not AOL?

So far I have discovered the cause of the roll off in phase observed in the blue trace of pic 2 of post 273. The pass transistor's Rce (?) combines with the 4.7u + 0.1u filter capacitance to introduce another pole into the bode plot. (Presumably there is a ESR zero as well. I will look again at the ESR of the 4.7u tantalum.) Makes sense.

I don't understand why the less than ideal supply for the op amp would boost LF loop gain. (And again why the change in loop gain isn't reflected in line rejection but hopefully I will get to that eventually...)

See attached bode plot to show the impact of deleting R9-C5-C6 and feeding U2 from an ideal 12V source (blue trace).

Counterintuitively - for me at least - an ideal 12V source for the op amp reduces line rejection in very high frequencies (above about 5MHz).

 

[Mark Johnson]

The pass transistor's (1/gm), which Bob Cordell calls re', interacts with output capacitance to make a pole. Paperback p.19, section "Transconductance", between Figure 2.2 and Figure 2.3.

The green vs blue IS fishy looking. Maybe you can figure out what's going on by .STEPping the value of R9 from 0.1R to 100R. This makes C5+C6 more and more "invisible" to the pass transistor.

Yes AOL, the open loop gain. My feeble memory failed me when I tried to recall the abbreviation in LTSPICE. Be sure to select the largest number "level" they offer on the pulldown menu, when customizing UniversalOpamp2.