Super Leach amp simulation woes

[spookydd]

Why not for predrivers, as I said these are what I would use:
KSA1220A/KSC2690A - to126 R-O-Y 160V 1.2A 20W 19pF 150MHz 220mA @50V 90mA @100V

A little beefier than the 2SA1381, but they have twice the capacitance, per fairchild datasheet, I see 26p typical. That may vary among sources.
Would that capacitance not be an issue?

What about reliable models? I don't have any known good ones.

 

[spookydd]

So the SOA rating plot is an overlay as I am following?

The SOA curves are in the plot file ahead of time, and stay there. The actual current plotted agains the Vce is on top of that, added after the sim has run.
The prepared plots have what's needed to go ahead with plotting the curves with the SOA already drawn up.

You must do the actual plot under some drive condition?

Nothing specific. It will attempt to draw the curve when running the sim, and of course would be wrong if attempted for a different type of analysis, like AC for example. In a case like that, the plot would want to switch to an other kind of analysis, which would remove the SOA plots in case of AC or noise analysis, but if a DC analysis was attempted, it would try to use the prepared definitions and it wouldn't mean anything useful.

So the only thing needed to have it work properly, is to run a transient as it was meant to be and prepared for that. Nothing beyond that. You can change all other things in the sim, like load, short, frequency, whatever...

Because all that is prepared, besides the tracing of the SOA chart and annotations, are the definition of what to plot on each axis, which is Ic on Y and the Vce on X.

As long as the plot file doesn't get overwritten, it can be reloaded at will.

And it does need to be either reloaded or at least refreshed because ltspice screws it all up when running the sim and doesn't put it back the way it was meant to be displayed.

Most of the time, I don't need to reload the plot file, only a space bar is enough to refresh it.

I have to think about this more, but I believe that you'd want to do it at about 39-40.5% of full power where dissipation in the output devices is a maximum.

Well, we can easily do that. I usually run sims at 1/3rd, 1/2 and 2/3rd output power to take a look at how dissipation evolves.

Taking the 2.3V input as a reference for nominal power, which is somewhat close, but not quite, to the true full power, we have about 300W on the 4ohms res load.
So aiming for about 120W would be roughly in the ballpark.
It takes 1.46V input to drive it to roughly that 120W output.

I put out the SOA plots at that level (posted). We're much lower than when clipping and when the glitches are there.
There are some glitches though, but nothing quite as bad.

I had to correct the power devices SOA plot file, since I named the important nodes, it all went wrong in the plot file, but now it will be stable with further changes.

To make sure you know which device each plot pertains to, just look at which Ic it's looking at for Y axis.

 

[spookydd]

I just zipped up the folder again, with the prepared plots and everything, the way the sim is now, with it ready to run as I just did to post the previous views.

Should run out of the box.

Just to see what happens with the prepared plot files, try to load them before running the sim.

Once the sim has run, while looking at the plot (window of it active), load up each prepared SOA plot file to look at power devices and then vas/predrivers.

To better understand how this really works behind the scene, load the plot files in a text editor.

I hope that little proggy Engauge will work soon, so I can start grabbing chart data more reliably.

 

[spookydd]

I'm just wondering if there is a correlation between capacitance and current carrying capacity in transistors.
Is this mostly true?
What I see is higher current capable ones have more capacitance. So am I seeing something that's not really there or is there something to it?
Big power devices do have a serious amount of capacitance, especially in comparison with the smaller ones as used for drivers and such...

 

[spookydd]

I found models from our friend keantoken:

.MODEL KSC2690A_k NPN ( IS=1.7783E-13 BF=132.5 NF=1.0 BR=8.495 NR=1.005 ISE=1.9953E-13 NE=1.5 ISC=1.5849E-9 NC=1.98 VAF=580.75 VAR=18.15 IKF=4.0271 IKR=0.0120 RB=2.98 RBM=0.001 IRB=0.6396 RE=0.0909 RC=1.4705 QCO=0 RCO=0 VO=6.587 GAMMA=2.8216E-7 CJE=4.0082E-10 VJE=0.6696 MJE=0.3296 FC=0.5 CJC=6.0404E-11 VJC=0.5 MJC=0.4266 XCJC=0.4955 XTB=1.2590 EG=1.2277 XTI=3.0 Tf=830p Vceo=160 Icrating=1.2A mfg=Fairchild)
.MODEL KSA1220A_k PNP (IS=4.7863E-13 BF=289.3 NF=1.0 BR=9.76 NR=1.006 ISE=5.2481E-12 NE=2 ISC=2.4909E-11 NC=1.5 VAF=98.5 VAR=6.7 IKF=2.7061 IKR=0.0759 RB=2.26 RBM=0.2308 IRB=0.001 RE=0.1908 RC=1.1748 QCO=0.02 RCO=3.9811 VO=11.078 GAMMA=5.01187E-8 CJE=3.4786E-10 VJE=0.9575 MJE=0.4694 FC=0.5 CJC=1.1224E-10 VJC=0.5761 MJC=0.4365 XCJC=0.4955 XTB=1.7978 EG=1.2255 XTI=3.0 Tf=970p Vceo=160 Icrating=1.2A mfg=Fairchild)

He's using those and he's doing good stuff with them, we can trust him as much as Bob for having checked his models for being as good as they can be.

 

[PB2]

Right a higher power/current device is larger and for the same type of process or all
things being equal the capacitance goes up.

I'd try Kean's models, if things go well stick with them. I think Kean states that he does
essentially a quick fix in my own words. I think he gets them in the ball park which from
my view is fine. I agree Kean is doing nice work.

Thanks for the input on SOA analysis. I was thinking from a power perspective but SOA
is really just current at a particular Vce (ignoring the pulsed ratings) so any input that
pushes the output to clipping should do it as I see it.

If the VAS has enough bias current to easily charge its own and the load capacitance it
should be fine. For a 1A device I'd call those low capacitance.

 

[spookydd]

I swapped the 4 pre-drivers to those other devices, leaving the vas as is, and tried it, with the same 4ohms res ld and 20khz as usual, and 2.3V input.

The open loop gain seems to have gone up slightly, but not much, however the phase margin went down quite a bit, and the gain margin up a little.
Phase margin remains at about 56deg though, so it would only take a small amount of tweaking on the compensation to get some of that back.

One other thing changed, thd went up a fair amount.

I don't have the SOA data handy, so that requires some work and time.

 

[PB2]

I'm familiar with those graph capturing tools but not quite following why you need them.
SOA curves are flat at the Ic limit, then power limited (Vce*Ic=Prated), then SOA limited
but usually also a straight line. Very rare that they are different.
But whatever makes it easy.

 

[spookydd]

I'd try Kean's models, if things go well stick with them.

I just did. It works, but some things have changed a bit. Nothing too drastic though.

SOA is really just current at a particular Vce (ignoring the pulsed ratings) so any input that pushes the output to clipping should do it as I see it.

Yes, any tran sim with those curves plotted will work, so any frequency, load or anything else can be examined. It's scary when we apply a short on the output, and we can see the huge violations, even when a VI limiter is there, trying to act as it was calculated, which to me, proves they don't work as well as they're supposed to, and that goes well against what Kiwanuka professes. (Am I going to get flamed for this? )

If the VAS has enough bias current to easily charge its own and the load capacitance it should be fine. For a 1A device I'd call those low capacitance.

Well I left the vas alone, changed only what's after it.
The capacitance is rather important for the vas isn't it?

 

[PB2]

These are ignorant statements as I pointed out in that thread on SOA, yet later on in the
thread mikeks gives himself a pat on the back, LOL. All it takes is a hot day for this
statement to be completely wrong - it has to be derated even with an infinite heat sink,
you know this but in case anyone else is reading:

Originally posted by BobEllis
Use enough heat sink to keep the junction temperature well within its rated limit and you don't have to worry about the derating factor.
Quote:

Originally posted by mikeks
I agree.

 

[spookydd]

I'm familiar with those graph capturing tools but not quite following why you need them.

Simply to get more accurate data and try to avoid too much guess work.
Most of those SOA plots have very thick curves and it's always hard to tell exactly where they cross or change direction. So I'm hoping the software will get it right better than my own eyes.

SOA curves are flat at the Ic limit, then power limited (Vce*Ic=Prated), then SOA limited but usually also a straight line. Very rare that they are different.

I just found it a bit difficult to guess the right spot where those curves change direction, and since it's almost always on log/log scales, when such an inflection point is somewhere between two grid lines, it's hard to guess exactly what the actual value is there. It's a best guess'timation...

I'll have to do this now for those new devices.

 

[spookydd]

it has to be derated even with an infinite heat sink,

My SOA prepared plots have a DC (or similar) added derated SOA line, which I made for a 50C rise (150C max junction for TO3s)

Of course that's an extreme limit not to reach, and the heatsinks have to be calculated to keep those cases at less than that 25+50=75C

The more headroom we keep the better of course, with more long term reliability in mind.

That's why for this superleach with 3055s, I'd be tempted to use 4 sets instead of 3 for the outputs. And the type of protection still needs to be thought of.

 

[PB2]

I think that using ideal power sources is fine for most of the analysis, but with short
circuit analysis adding a realistic PSU source resistance will help a lot.

As I followed you, you want the SOA protection to cover a short? I don't think that's
easy to do properly and reliably. It doesn't make any sound with a short so why not
put it into protect? There is a thread on here about DIY protection have you seen it?

I don't think that simple transistor SOA protection can be expected to allow the amp to
sort of ride the SOA curve with any sort of precision. But if set to protect say at .5 ohms
and below might at least save the devices under adverse conditions.

 

[PB2]

I agree on the 4 sets of outputs but I'd leave this sim at 3 since the MJLs have more
capacitance than the actual devices.

I re-read Bob's SPICE section and I need to think about it a bit more but I have some new
thoughts. Why not start with Bob's MJL models, adjust beta to the correct peak value and
adjust the parameter that controls droop at high current for the best match. We are not
really concerned with low Ic droop of beta so just leave it, that way you only have two
parameters to iterate for hfe. Then adjust the junction capacitances to the correct value,
and TF for the correct Ft 2-2.5 ish should be fine. I need to think about this a bit more but
for now it seems to be good enough and closer to reality. Beta droop at high Ic is most
important.

 

[PB2]

Simply to get more accurate data and try to avoid too much guess work.
Most of those SOA plots have very thick curves and it's always hard to tell exactly where they cross or change direction. So I'm hoping the software will get it right better than my own eyes.



I just found it a bit difficult to guess the right spot where those curves change direction, and since it's almost always on log/log scales, when such an inflection point is somewhere between two grid lines, it's hard to guess exactly what the actual value is there. It's a best guess'timation...

I'll have to do this now for those new devices.

I agree but, for example, I was looking at the 2N3055 on the constant power section of the
curve thinking that at 40V the curve was very close to 3A but obviously the correct value is
115/40 = 2.875A.

 

[PB2]

Stepping back for a minute, as I understood it you were interested in the Leach because
many have been built it (is a proven design) and your impression was that it was low
distortion. Knowing now, that it has oscillated for several people, and that it has higher
distortion would you want to pick a different front end?
All you analysis of the output stage would still apply to any front end that you choose.

People seem to speak highly of roender designs, RMI-FC100 MKII or whatever.

 

[spookydd]

I think that using ideal power sources is fine for most of the analysis, but with short circuit analysis adding a realistic PSU source resistance will help a lot.

I usually have resistance added, along with large caps, on the psu. In this sim, they got removed earlier, but I can add that back.

I usually have that in the order of 100mohms or so, sometimes more for smaller psus. Should that be more?

As I followed you, you want the SOA protection to cover a short?

Well, the shorts are just a part of it. I tried it with lower and lower impedance, to account for possible misuse of the amp with too many paralleled complex loads.
The shorts are sometimes not a dead short, with some resistance, sometimes even made temporary by a fusible piece of wire that the amp will blow up and then the short is removed by force.

I don't think that's easy to do properly and reliably.

That seems to be the case, having looked at many possible methods.

And that's why I've been interested in many other methods besides the simple limiters, and I think a combination of more than one method is required for proper protection.

It doesn't make any sound with a short so why not put it into protect?

That's true, but a protect mode that sticks that way even once the fault is removed isn't something I want in an amp. That may be ok for many, but I don't want an amp that completely stops on a short and that requires any action such as power cycling to reset it.

A thermal sensing should be done and be used as well, and I really think a good thing to have, along with the limiters is an input level limiter (compressor), that brings down the input drive to prevent further excursion into overdrive.

I think that when a short on the output is removed, the amp should just resume its work and hopefully, if properly protected and designed, do so without any adverse effects.

Of course this is more in line with P.A than HiFi, but that's how I prefer using amps.

For example, one of my long time projects, of much larger scale, is for a 4 way active system, with input signal detection, that triggers the power up sequence to get all the amps and filters properly powered up, without overtaxing the mains, and it would have no knobs, no switches, and it would be a single rack on wheels placed very close to the speakers, with the shortest speaker cables possible.

That obviates this type of handling of faults.

This isn't necessarily what this superamp project needs, but I prefer this kind of feature.

There is a thread on here about DIY protection have you seen it?

I may have. I've seen a lot of stuff, but we have a huge wealth of posting history and it's kind of hard to have seen it all.

Maybe you can point to it here, and many can look as well.

I don't think that simple transistor SOA protection can be expected to allow the amp to sort of ride the SOA curve with any sort of precision.

Seems unlikely, and that's why I really am thinking about the input limiter as well, to use together.

The limiter can have a small fallback effect, if possible, as long as no pumping effect is caused, or at least keep the drive signal from going higher.

But if set to protect say at .5 ohms and below might at least save the devices under adverse conditions.

So far, almost all of the sims I've done in that area have shown that even at such low impedance, the limiters fail to keep within SOA.

The only one I simed that worked, was one of McIntosh's design, which has a largely overbuilt output stage, with far more available SOA than needed, which is right along the lines of what I was saying earlier, that to make such a limiter to work well enough, far more pairs are needed than really required.

 

[spookydd]

Why not start with Bob's MJL models, adjust beta to the correct peak value and adjust the parameter that controls droop at high current for the best match.

It doesn't work quite that way. It's not like we have specific parameters to act on this kind of specific behavior.

I've been playing with this lately, and it hasn't been that straightforward.
There is the parameter that controls where the rolloff starts (very fuzzy) IKF, but nothing to control how fast the rolloff is, and I found I couldn't get the highest point of the curve where it needs to be.
Then playing a bit with the IS acts on the small current rolloff, but we can't really control where it happens, just its magnitude.

It's much more intricate than this, so not so simple. I'm working on it, but so far it's hard to get it right.

Then adjust the junction capacitances to the correct value,

For the 3055, my tweaking ended up with 300p for CJC, which seems about right. And CJE could be a little more.

and TF for the correct Ft 2-2.5 ish should be fine.

TF is a time and not a frequency, so it's a little tricky to find a good value because it also interacts with other things. Once you set that for a value that seems fine, then acting on other parameters screw that up.

Most 3055 datasheets state 2.5Mhz minimum, with the max at 6Mhz.
Curiously the PNPs are faster.

My tweaking led me to use 60n for TF and I couldn't figure out what TR should be.

However, there is also VAF to think about, which has to be quite different.
For the 3055, VAF at 150 seems like a good compromise.

But there are other parms that would also make some difference, such as the series resistance on each leg (EBC), and things like ISE and ISC (which also interact with XCJC/MJC).

So much to tweak.

 

[spookydd]

Knowing now, that it has oscillated for several people, and that it has higher distortion would you want to pick a different front end?

Would the front end be a factor in this? Really?

I'm usually more inclined to use more standard dual ltp with current source and mirrors, and then sometimes either sziklai or cascode.

All you analysis of the output stage would still apply to any front end that you choose.

What topo would you have in mind?

People seem to speak highly of roender designs, RMI-FC100 MKII or whatever.

I don't recall this. What kind of topo is this?

One thing I was curious about, especially since the change in the pre-drivers, was to cascode the vas.

But I'm not convinced that front end is what's bringing in much trouble.
We can go for a more common cascoding method there, but I think current sources and mirrors might do some good too.

 

[spookydd]

I'm just thinking, if altering things like adding a cascode to the vas, changing the front end for something with mirrors and sources, cascode, sziklai or whatever, what we get is far more gain. Essentially transforming the leach concept of low open loop gain back into a larger open loop gain, which obviously would work towards lowering thd a lot.
But then leach's main concept of reducing tim goes out of the window.
However, in the more recent past, some people have found out that some of this concept was not quite right for low tim, although it did work in that direction, some think it's not necessary to have low open loop gain for lower tim.

As far as I understand it, the tim occurs when the front end gets taken "by surprise" by fast transients on the input, and the lag from the feedback comes too late to get the correction to work. And also the front end must never be put in a situation where it can saturate, which is why leach put so much degen there.

But I'm thinking maybe he went a tad overboard on that.