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"Reference" TDA1541A DAC with I2S-BUS architecture

Surface Finish for future PCB´s

  • ENIG - Electroless Nickle/Immersion Gold

    Votes: 93 48.7%

  • Immersion Silver

    Votes: 54 28.3%

  • Immersion Tin

    Votes: 24 12.6%

  • OSP - Organic Solderability Preservatives

    Votes: 20 10.5%
  • Total voters
    191
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beardman

Member
Joined 2005
Hello
Sorry i do not know so much about digital,,few question
shall i use the DEM chip when i will use DDdac spdif to i2s converter ??
what are the DEM chip for ??
is it ok to make the i-v resistor so high ,that i kan have 3v out ? (i use 6n2p Lampi for output ) i use now 75ohm for my pcm1794 --
Best Bjarne
 
dvb projekt

dvb projekt

Member
Joined 2009
Paid Member
beardman said:
Hello
Sorry i do not know so much about digital,,few question
shall i use the DEM chip when i will use DDdac spdif to i2s converter ??
what are the DEM chip for ??
is it ok to make the i-v resistor so high ,that i kan have 3v out ? (i use 6n2p Lampi for output ) i use now 75ohm for my pcm1794 --
Best Bjarne
Click to expand...

merlin2069er said:
I'd like to know as well.
Click to expand...

To get the maximum performance use all new modifications: Free running DEM oscillator mod. & 3.3V I2S attenuator mod.

You will find all informations about this mods in -ecdesigns- thread.

If you use a tube I/V stage, you should do also the bandwidth limiting mod. The recommended R I/V value for one TDA1541A here is ~56R.

Best regards,
Oliver

:wave:
 
LucasAdamson

LucasAdamson

Member
Joined 2009
Hi Oliver,

Regarding the mod to put SMD caps across the TDA1541 outputs to reduce bandwidth for distortion reduction at the SRPP 6n2p tubes on Tubizator, can I ask your advice please?

My two TDA1541A boards are modified Mk1 boards, and are soldered together with output wires, i2s wires etc., so access to the output of the chips is impossible for me, or at least undesirable. Is there a way to solder an alternative SMD cap across the inputs of the Tubizator? What size would that be for a 2 chip dac please?

Thanks
 
dvb projekt

dvb projekt

Member
Joined 2009
Paid Member
LucasAdamson said:
Hi Oliver,

Regarding the mod to put SMD caps across the TDA1541 outputs to reduce bandwidth for distortion reduction at the SRPP 6n2p tubes on Tubizator, can I ask your advice please?

My two TDA1541A boards are modified Mk1 boards, and are soldered together with output wires, i2s wires etc., so access to the output of the chips is impossible for me, or at least undesirable. Is there a way to solder an alternative SMD cap across the inputs of the Tubizator? What size would that be for a 2 chip dac please?

Thanks
Click to expand...

Hi Lucas,

John recommend to set the corner turnover frequency to 300...400 KHz. You could calculate the cap value with this online calculator.

If you have the recommended R I/V value of 28R (2x56R parallel) and could only solder two caps, than you should use a pair of 0.015µF SMD caps. Mouser Part No.: 667-ECH-U1H153GX5

These caps should be soldered as near as possible to the Pin 6 (AOR) & 5 and Pin 25 (AOL) and 5 of the TDA1541A, e.g. downside of one MK1 pcb.


merlin2069er said:
hmm, looks like you don't add the caps in your reference psu.
But there are spots for 8 caps right by the diodes there. Is this where the .1uf wima caps go? (I got 16 of them).
Click to expand...

Yes, that´s the place where you could solder these caps!

:wave:
 
andrea_mori

andrea_mori

Banned
Joined 2005
beardman said:
Hello
Is the spif to i2s converter from DDdac ok to use with the Red Baron ??
or are there other way to go
best Bjarne
Click to expand...

I would suggest to use Ian's Fifo buffer with its S/PDIF converter, so you can totally isolate the source.
I'm planning to use Ian's Fifo without the reclock board, running at 128fs (5.6448 MHz), avoiding any clock divider.
Ian's Fifo buffer provides 2 words of 64 bit each at 128fs (16 bit of music and 48 trailing zeros). The TDA1541 can run at 5.6448 MHz in NOS mode, discarding the trailing zeros.
In this way, one can provide the BCK directly to the DAC pin from the MCLK, minimizing jitter. The same MCLK is sent back to the Fifo buffer synchronizing the system, isolated from the source.
The only problem is to find an XO at 5.6448 MHz (I'm developing it myself).
 
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