One could perhaps disconnect the output of the Si clock so that the firmware still sees it. One could then attach an alternate clock to the point where the Si output used to connect. So long as the input is clocked to that same clock, the dac should be stable and synchronous. What might be a complication would be to switch clock frequencies when needed from 44.1kHz family sample rates to 48kHz family. If the only hint of that is in I2C programming of the Si clock, then the I2C bus might have to be monitored with an MCU to detect when to switch frequencies. 
Regarding WC and or embedded clocks (such as AES/SPDIF/TOSLINK), they require a PLL to track the incoming clock or they need ASRC to resample incoming digital audio to a stable internal clock. Neither of the above are ideal, but they are the only options when real-time playback is required for professional use. (In other words, when FIFO delay is not an option.)
Of the two viable options, IMHO high quality ASRC is probably the best choice.
Of the two viable options, IMHO high quality ASRC is probably the best choice.
One could perhaps disconnect the output of the Si clock so that the firmware still sees it. One could then attach an alternate clock to the point where the Si output used to connect. So long as the input is clocked to that same clock, the dac should be stable and synchronous. What might be a complication would be to switch clock frequencies when needed from 44.1kHz family sample rates to 48kHz family. If the only hint of that is in I2C programming of the Si clock, then the I2C bus might have to be monitored with an MCU to detect when to switch frequencies.
Haven't heard anyone do this... if one broke the clock trace, injected a new clock there, which in turn synchronised the "driver" (usb board, some spdif source) - it could work I suppose. Maybe someone did it?? Stiffoperated to 44,1 - I could live with that...
For "new customers", it would be easier to get a DAM with built in USB...
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And do
Not that I wouldn’t welcome dedicated XO’s but it’s clear to me that Soren has different ideas about architecture. Which is also fine for me. Very much looking forward to andrea’s ABX testing methodology and results.
As I said elsewhere, I’m a critical listener and easily discern between good and great but doubt to have the golden ear to pick out a femtoclock from a picoclock.
Not that I wouldn’t welcome dedicated XO’s but it’s clear to me that Soren has different ideas about architecture. Which is also fine for me. Very much looking forward to andrea’s ABX testing methodology and results.
As I said elsewhere, I’m a critical listener and easily discern between good and great but doubt to have the golden ear to pick out a femtoclock from a picoclock.
If you skip spdif, everything becomes so much easier...
Time to skip this legacy interface for more serious business. Look at Apple, they have no fear of dropping what seems to be impossible "to live without" - like ethernet etc..
Btw - ethernet based audio in consumer gear is something I look forward to.
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Time to skip this legacy interface for more serious business. Look at Apple, they have no fear of dropping what seems to be impossible "to live without" - like ethernet etc..
Btw - ethernet based audio in consumer gear is something I look forward to.
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And do
+1
If anyone didn't see it yet https://www.superbestaudiofriends.org/index.php?threads/soekris-dac2541-technical-measurements.10561
Jitter suppression on the next-gen dac/amp (non-DAM) is really good. I do believe Soren knows what he's doing...
I guess that the jitter suppression is as good in the 1021. Same DPLL and short fifo. Just confirms that what we might hear as "coming thru" is not jitter but something else. Most probably the incoming clocks frequency variation (wander) and how that effects the behaviour of the DPLL... But jitter, it aint
The measurements comments seem to miss the potential close in phase noise behaviour of the Si5xx? See picture. This is a result of the clock changing or/and the less stellar close in PN from the Si. But again - it aint coming from outside - the fifo kills all incoming jitter but passes wander. All "problems" are "domestic"... On the other hand - the title says "Jitter Suppression" - suppression being the interesting world indicating that this is not focusing on total jitter but rather what is suppressed from the outside - now the measurement cant sort out what comes from where so... intrinsic jitter is in the graph too. It is hard.
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Attachments
VERY nice and much improved from the 1541 measurements here:
Review and Measurements of Soekris dac1421 Multibit DAC | Page 5 | Audio Science Review (ASR) Forum
Wondering what the basis for that improvement is. Mostly power supply?
Not if you let the clock inside follow the wander. This is exactly what is happening in the DAM. If you look some pages back, you can see zfe measurements on this.
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