Andrea, I never said I disagree with your technical opinion and I even complemented your work and the speed you are moving foreward... but I disagree in the way you bring it.
Since you ask about my technical opinion, well for your super-duper own design, a fifo should not be needed at all and it is making everything unnecessarily more complex. Manage the problem at the source and don't use patches. With your skills and ideology, I don't understand why you would mess around with it between your SD-player and your dac, make the SD-player slave. For all other sources: asynchronous USB should do it and stays versatile, even for your jittery-by-design Rpi. If you invest your technical opinions in a super-duper USB interface, I might even be tempted.
Since you ask about my technical opinion, well for your super-duper own design, a fifo should not be needed at all and it is making everything unnecessarily more complex. Manage the problem at the source and don't use patches. With your skills and ideology, I don't understand why you would mess around with it between your SD-player and your dac, make the SD-player slave. For all other sources: asynchronous USB should do it and stays versatile, even for your jittery-by-design Rpi. If you invest your technical opinions in a super-duper USB interface, I might even be tempted.
Sorry but you cannot install another clock on the DAM1021, it does not provides support for external clock.
If you want the DAM1021 to support external clock please ask the designer, it's not me, I cannot access hardware and software design of this DAC.
About another PLL I have already said, I would never use a PLL in audio to digital conversion.
You are free to follow this way but you cannot ask me to follow your way since I totally disagree.
And yes, I will feed the DAC part of the DAM (resistors ladder and switches).
Is it so difficult to understand that I don't agree with the front-end design choices?
Neither MSB Tech does agree with the DAM front-end approach since they have used our approach, so would you ask them to redesign their DAC in the DAM way?
I don't, so as you can see I would not redesign all DAC, and I don't understand what other DAC you are referring.
I agree with you, for those who cannot accept the FIFO latency the asynchronous USB is the best solution.
Master clock DAC side and USB to I2S device slaved to the DAC master clock.
This way the source does not affect the DAC that will run with a clean clock (if well isolated).
The DAM does not work this way and I cannot design an interface to get it working this way.
The FIFO buffer is the alternative way to get the best isolation between the DAC and the source.
We have chosen this second way because it's not limited to USB source, it can accept whatever I2S source isolating it from the DAC.
Resistors ladder and switches are not the complete DAM "DAC part". The DAM DAC part consists also of 2-stage oversampling / filtering as well as the sign-magnitude strategy.
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It is not an opinion, its a fact that the DAM DAC uses OS and filters and if you take them away, you cant call it a DAM DAC any longer. Thats basic logic.
You wrote previously:
"I thought it was clear, I wrote several times that I don't agree about the design choices of the DAM1021's front end.
IMHO there is a better way to feed the DAC so our upgrade follows our different approach (the FIFO Lite).
I will also measure the phase noise and the ladder accuracy of the DAM before and after the upgrade, since we trust more in this kind of measurements rather than the THD."
You are confusing a ladder and some registers with a DAC. Register and resistors don't make a DAC. You cant do the DAMenstien operation and then say - hey look (listen), now the DAM DAC sound much better...
what you can say is:
If you take the resistors and som logic from a DAM DAC board and control that part with my new parts, and the result sounds better (if it will....)
Why I'm asking you if you will do redesign of other DACs is that you seem to want to re-design DACs that you don't "agree with". I was curious if you "agree" with the design of all other DACs than the DAM? And if not - will you re-design also other DACs. All this is logic, drawn from your previous statements.
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Again, the TDA1541 and the AD1862 do not contains OS and filters and they are just DAC.
They contain the logic to convert the incoming signals, the switches and the ladder.
So in my opinion they are DAC, and even in our opinion the front end is another thing.
And again tell me what DAC I should redesign so I will let you know.
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Sure, I'm with you on the performance constraints that the Si clocks impose.
Other than though what's the difference in architecture? Yes I see the dedicated XO's, which may be miles ahead of the Si's, with galvanic isolation from the FPGA. But otherwise it's still FIFO in the FPGA, dirty I2S in, reclocked out, which seems the same to me?
The dam1121 does but still expects a programmable clock. (Why not just ignore it and switch clocks based off some external detection or control? The dam1121 thread has experiments on this front -- so far not 100% successful.)
No, it's not the same approach, in our FIFO the most crucial signal for a DAC like the DAM (the LRCK) comes directly from the oscillators, it does not cross the FPGA so it's not dirty, it's as clean as possible.
The DAM expects a Si programmable oscillator with its protocol since I cannot access the firmware.
And again I would never use a PLL in a DAC, this is my point of view.