Folks, I'd like an opinion please. The question is this:
When I lay out the silk screen, do people like to see the component value marked in the device body (this will be covered by the device when the board is stuffed, just intended as an aid during stuffing) and the designator placed so that it is visible when the board is stuffed, or is just the schematic designator only preferred?
When I lay out the silk screen, do people like to see the component value marked in the device body (this will be covered by the device when the board is stuffed, just intended as an aid during stuffing) and the designator placed so that it is visible when the board is stuffed, or is just the schematic designator only preferred?
Hi Jason,
I always place the comp ref des in silk somewhere on the comp perimeter, even when I make the footprint. Genrally, on the assy drawing layer, I place both value and ref des inside the comp body or the assy ref des to match where it is in silk layer.
For tight placement say 0805 or smaller it becomes a lot more work or impossible if it is too dense. Have to refer to the assy drawing or layout. The smallest silk text height I use is 50mil with a 5-6 mil line width.
Been doing this way for years without fail. You find these things out when you have to test your own creation and are pissed when you don't do it right correctly. It never hurts to add more information to the silk layer, to help guide you, when your memory fails you.
Rick
I always place the comp ref des in silk somewhere on the comp perimeter, even when I make the footprint. Genrally, on the assy drawing layer, I place both value and ref des inside the comp body or the assy ref des to match where it is in silk layer.
For tight placement say 0805 or smaller it becomes a lot more work or impossible if it is too dense. Have to refer to the assy drawing or layout. The smallest silk text height I use is 50mil with a 5-6 mil line width.
Been doing this way for years without fail. You find these things out when you have to test your own creation and are pissed when you don't do it right correctly. It never hurts to add more information to the silk layer, to help guide you, when your memory fails you.
Rick
Yes, I'm talking about the schematic reference being visible when the component is installed, but putting the value underneath as a stuffing aid.
Nigel, that is just cheating 
having a spare un-populated pcb in your hand.
I remember doing some dense pcb's, we had to put a 21" monitor in the lab, so we could be able to tracing signals using cross-hilighting of comps/nets in the schematic, to where they were placed and routed on the mutli-layer pcb. This is a good as it gets.
Good feedback everyone.
having a spare un-populated pcb in your hand. I remember doing some dense pcb's, we had to put a 21" monitor in the lab, so we could be able to tracing signals using cross-hilighting of comps/nets in the schematic, to where they were placed and routed on the mutli-layer pcb. This is a good as it gets.
Good feedback everyone.
pretty old thread , but how abt this for a layout? I generally try to keep all traces as short as possible and thicker whenever required.
This layout already posted in APEX 100w ultimate amp thread, but re-posting here for convenience. Its an APEX design , servo pre-amp PSU.
any critic is welcome.
remember its a single side layout, I tried to optimize as much as possible.
JKT, some of your designs helped me learn.
regards
Prasi
This layout already posted in APEX 100w ultimate amp thread, but re-posting here for convenience. Its an APEX design , servo pre-amp PSU.
any critic is welcome.
remember its a single side layout, I tried to optimize as much as possible.
JKT, some of your designs helped me learn.
regards
Prasi
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I could provide smd option on the bottom for C7, C8 like done for the op amp power pins.
