Output transistor safe operating area

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I like the IRFP240/9240 devices and have had good experiences with them so long as you dont short them out.

I like these devices also. They are very good for the money, and are capable of very good performance in a goo design. They definitely need fast short circuit protection because they will conduct 30A in the blink of an eye. I have measured their destruct SOA, and it is about twice what their SOA curves show. BTW, this should not be a surprize because the SOA curves for these MOSFETs basically define peak allowable junction temperature, and that is for long-term reliability. Destruct point is quite a bit higher.

The Toshiba devices are better, in my opinion, but they cost about 4 times as much.

TrenchFETs have something approaching a second breakdown nature that can make them more vulnerable in linear applications. I think it has to do with very localized current hogging. They have a much higher current at which their TCvgs goes through zero, and very high transconductance, both of which probably are responsible in part for some of their secondary breakdown-like behavior. I seem to rememember studying them a year or so ago and concluded that I would not recommend them for audio for a number of reasons.

They are phenomenal for switching applications.

Cheers,
Bob
 
This is a tough question to answer. I always prefer datasheets that show SOA for DC and a variety of pulse times. For audio purposes, I would assume that 1 second SOA is about the same as DC SOA. Audio excursions that stress SOA will normally be fairly brief. Bear in mind that the period of a 20 Hz sinusoid is 50 ms, and that even a quarter cycle is only 12.5 ms. In the absence of short-circuit issues, a 10 ms SOA is probably the most relevant to audio when driving a loudspeaker.

Another thing I like to see on datasheets, but which is often only presented on MOSFET datasheets, is transient thermal impedance. This can sometimes give a hint as to the relationship of DC SOA to pulsed SOA.

Cheers,
Bob

Hi Bob,

Most of the pulsed curves are spec'd as being non-repetitive or for low duty cycles such as 10% for example and I've always used the DC or 1 sec times for this reason. The pulsed values would apply IMO for tripping a safety circuit with a hold state or a fuse. Refer to the tabulated Second Breakdown data here where it is called out as non-repetitive:
http://www.onsemi.com/pub_link/Collateral/MJ21193-D.PDF

It would be interesting to know what the repetitive pulsed values might be say for a 50% duty cycle. I could see using the 100 mS pulsed value in place of the 10 mS in situations where we do not meet the 10% duty cycle rule.
 
Hi Bob,

Most of the pulsed curves are spec'd as being non-repetitive or for low duty cycles such as 10% for example and I've always used the DC or 1 sec times for this reason. The pulsed values would apply IMO for tripping a safety circuit with a hold state or a fuse. Refer to the tabulated Second Breakdown data here where it is called out as non-repetitive:
http://www.onsemi.com/pub_link/Collateral/MJ21193-D.PDF

It would be interesting to know what the repetitive pulsed values might be say for a 50% duty cycle. I could see using the 100 mS pulsed value in place of the 10 mS in situations where we do not meet the 10% duty cycle rule.

Bear in mind that the non-repetitive statement is also there to keep average dissipation from building up. The manufacturers have to err on the side of conservatism to cover all situations without going into deep detail. I think typical audio excursions into territory near the SOA boundary would have a duty cycle less than, say, 25%. Bear in mind that in class AB, signal excursions cannot generally ever go much beyond 50%.

Cheers,
Bob
 
The DC peak current rating is usually limited by the bond wires, the continuous rating is the die design limit.

The usual 150C limit is caused by the plastic packaging, as Zetex used a higher temperature rated plastic and was able to take the rating to about 200C and increase the dissipation limit of their packages that way. Zetex grew out of Ferranti in Oldham near Manchester in the UK.

The usual Jedec specs call for a 300uSec pulse to measure the parameters of the devices, so that is what is used on the production lines and explains why there are usually more parameters measured at those pulse widths.

A torture test that was used by a company I used to work for was to run 15 Amps through a 5 mH coil through the "transistor" under test, then the transistor was given a hard turnoff and the breakdown volts were measured for the whole breakdown to confirm a good die attach to the device, it was actually a darlington with resistors that were zener zapped to define gain, and the breakdown was held to tight limits by zener zapping the breakdown setting zeners.

The second breakdown is current crowding that causes localised heating that can destroy small spots within the transistor, can be seen if the top is sawn/dissolved off.
 
Bear in mind that the non-repetitive statement is also there to keep average dissipation from building up. The manufacturers have to err on the side of conservatism to cover all situations without going into deep detail.
Bob

I believe that the issue is that once you exceed the DC portion of the s/b curve we are at a point where localized thermal runaway will occur and therefore it is important to have a period of time where the temp sufficiently equalizes across the die. The DC portion of the s/b curve is where heating is localized with higher current concentration in that area causing the part to act as a smaller part with lower max power but there is no risk of thermal runaway. Anywhere beyond DC and there is a risk as I see it. I believe that it is more than just average dissipation.

I think typical audio excursions into territory near the SOA boundary would have a duty cycle less than, say, 25%. Bear in mind that in class AB, signal excursions cannot generally ever go much beyond 50%.

By 50% you mean with an AC coupled amp? I'd agree that this is reasonable and is what I use for calculating Pdiss under signal conditions. There are many music waveforms that are roughly square, or a clipped signal that would exceed the 25% number. I do see the point that if we design for absolute worst case we usually end up with an over designed amp.
On the other hand I believe that there are many amps that survive only because there is some margin in those numbers.

This discussion sure brings back memories from when my older brother went off to EE school in the 1970s and I told him to figure out why the Tiger amps blew up, LOL. We had a lot of discussions about loop stability, and SOA.
 
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I believe that the issue is that once you exceed the DC portion of the s/b curve we are at a point where localized thermal runaway will occur and therefore it is important to have a period of time where the temp sufficiently equalizes across the die. The DC portion of the s/b curve is where heating is localized with higher current concentration in that area causing the part to act as a smaller part with lower max power but there is no risk of thermal runaway. Anywhere beyond DC and there is a risk as I see it. I believe that it is more than just average dissipation.



By 50% you mean with an AC coupled amp? I'd agree that this is reasonable and is what I use for calculating Pdiss under signal conditions. There are many music waveforms that are roughly square, or a clipped signal that would exceed the 25% number. I do see the point that if we design for absolute worst case we usually end up with an over designed amp.
On the other hand I believe that there are many amps that survive only because there is some margin in those numbers.

This discussion sure brings back memories from when my older brother went off to EE school in the 1970s and I told him to figure out why the Tiger amps blew up, LOL. We had a lot of discussions about loop stability, and SOA.

We need to distinguish between reasons why manufacturers spec something a certain way and the risks or mechanisms of second breakdown. I was addressing the reason why they use the word non-repetive. I was not trying to minimize the risk. Second breakdown is a fast thermal effect, and you are right about the need for the localized hot sopt site to cool down before being energized again.

However, how often is "non-repetitive"? Once in the lifetime of the device? Once a second? How long does the site take to cool down so that it doesn't remember the last time it got zapped? That is the question. The die thermal time constant is a good guide in this. It is usually on the order of 20 ms.

So perhaps they should have specified some minimum time gap between pulses. Strictly non-repetitive is a bit extreme.

There is certainly always risk with SOA excursions, I agree. What I meant in regard to average dissipation being a reason for the non-repetitive statement has to do with the fact that SOA pulses often can drive the part to high instantaneous dissipation, which will turn into high average dissipation if the pulse is repeated too often. Who knows, without the non-repetitive language, someone might think they can apply a 10 ms pulse and only have it off for 1 ms. :).

Cheers,
Bob
 
As I previously stated several manufacturers quote a 10% duty cycle for the pulse which says to me that this is because the number they quote is a true max, and that it needs a long relative time to get back to the steady state.

I don't want to argue with you, I just wanted to understand your thinking as to how you were getting around the non-repetitive part.

You say use the 10mS spec for audio, I say use the 100mS spec for events that last up to 10 or 20 mS but have a duty cycle higher than 10% as a rough guideline. I should also mention that there is a fairly large difference between the 100 mS and the 10mS specs.
 
Bitrex
You want to know how to calculate Safe Operating Area? OK, this is what you do. First determine the minimum load impedance. Now multiply the output power desired by the load. Let’s say 100 watts at 2 ohms =200, now take the square root of 200 you get 14.14 volts. Now multiply the output voltage 14.14 times 1.414 to get the peak output voltage of 20V, next determine the losses from the power supply sagging and the voltage dropped across the output devices to determine your rail voltage. Let’s say +/- 28v. Now take 100 watts and divide it by 2 ohms = 50, now take the square root of that and you now have your output current, which is 7.07A.
Here is the formula: Vcc – Vpk = Vce @ A x -30 degree (I am using -30 degrees as the phase shift angle, purely resistive would be 0 degrees and purely inductive is -90 degrees phase shift. I have found 30 degrees is a good approximation of the actual load. 90 degrees = 60 degrees, calculate this by 60 sin x A ‘the output current’), 60 sin x 7.07A = 6.123A. I normally do this at V @ 90degrees, 120 degrees, 150 degrees and 180 degrees, with current calculated at 60 degrees, 90 degrees, 120 degrees and 150 degrees.
We have: Vcc = 28V
Vo pk = 20V
Ao = 7.07A
Load = 2 ohms

Vcc – Vo pk = V ce @ -30 degrees x A

90 degrees: 28v – 20v = 8v @ 60 sin 7,07 = 6.123A
120 degrees: 28v – 17.32v = 10.68v @ 90 sin x 7.07 = 7.07A
150 degrees: 28v - 10v = 18v @ 120 sin x 7.07 = 6.123A
180 degrees: 28v - 0v = 28v @ 150 sin x 7.07 = 3.535A

There are also some tricks you can use to improve the Safe Operating Area of the output devices. Like instead of 1 Hz find out the SOA is at 100ms, the current of the SOA will increase about 1.3 times. Just put in a second order filter and adjust it to be 8dB down at 10Hz.. You will end up with a sight roll off at 20Hz, about 1 dB or +/- .5 dB. If you use a steeper filter say 18 dB you will end up with an amp that’s flat @ 20Hz.
I looked at the SOA chart from the transistor someone was talking about MJL21193. The SOA chart on the PDF for this part is pretty poor, all it shows is 1Hz.
 
As I previously stated several manufacturers quote a 10% duty cycle for the pulse which says to me that this is because the number they quote is a true max, and that it needs a long relative time to get back to the steady state.

I don't want to argue with you, I just wanted to understand your thinking as to how you were getting around the non-repetitive part.

You say use the 10mS spec for audio, I say use the 100mS spec for events that last up to 10 or 20 mS but have a duty cycle higher than 10% as a rough guideline. I should also mention that there is a fairly large difference between the 100 mS and the 10mS specs.

No problem. It never hurts to err on the conservative side. I think I just got too wrapped up in the "non-repetitive" language that some use in the spec sheet. I usually focus on the 100 ms number anyway in practice. The SOA problem is very real. BTW, too many people ignore the required SOA of the driver transistors, and in some cases they can go first and then take the output transistors with them.

I address a number of these issues in my book. One of the most interesting discussions there is the SOA boundary that is formed by overlapped elliptical load lines with different phase angles where the resistive component of the load impedance is held constant.

Cheers,
Bob
 
IMO we always need to start analysis with something like this, for various loads and input signals.
 

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David Eather discusses this in detail for both output and driver devices.
He goes on to show a hand calculation method that takes account of load phase angle and shows how to plot the results to compare to the manufacturer's datasheet SOA Lines.

Bensen did a spreadsheet for us that automates all the arithmetic and plotting to make it very easy to "see" how the proposed amplifier will "stress" the devices cf. the datasheet.

I have modified Bensen's spreadsheet to also include BJT output devices and BJT driver devices and de-rate devices for operational Tc. For some output devices I have included protection locus using Jens' modified version of the Leach protection circuit.

If anyone wants any or all 3 sets of excel spreadsheets then Email me.
 
I don't understand the parts where you are considering the load phase angle.
Can you explain more?
Have you read David Eather?
AndrewT,
I have not read anything by David Eather, but I would like to. Can you tell me where I can find his articles. Is his explanation different than mine? I have been designing Home Audio amplifiers, Car Audio amplifiers, Guitar amplifiers and Professional Audio amplifiers for 30 years. The formula I published is the same I used for designing all of them.
Now, as far as the phase shift goes, a purely resistive load voltage and currant are both in phase, 0 degrees of phase shift. A pure inductor the voltage is at 0 degrees phase but the current is shifted 90 degrees. A typical voice coil has both resistive and inductive qualities. -45 degrees would be the center point of phase shift but in most voice coils are slightly more resistive than inductive, which gives you a phase shift angle of -30 degrees. If you have any other questions please feel free to contact me.

Thanks, Ace956
 
David Eather's SOA paper

Hi,
here's copies from quite a while ago.

BTW,
I use 45degrees of load phase for moderate speaker reactance and 60degrees of load phase for severe speaker reactance.
This does not include extreme reactance speakers
 

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AndrewT,
I looked over the work of David Esther's and he is basicly saying the exact same thing as I did in m formula just stated a little deifferently. Either formula will work. I was working on the heat sink slection process but I see that he has already addressed that.

thanks, Wade
 
AndrewT,
One more thing about David's papers is the phase shift. I have always used -30* phase shift. I have designed and manufactured thousands of amplifiers using this phase angle. David on the other hand suggests using -45* to _60*. this will work fine but it will require that you use more transistors for the same output power. Like I said -30* has always worked for me.

Thanke, Wade
 
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